Staff Design Verification Engineer (DV) / Senior Staff Design Verification Engineer (DV)ID:59121

10,000 MYR ~ 30,000 MYR峇六拜 Bayan Lepas6日 ago

概述

  • 薪资

    10,000 MYR ~ 30,000 MYR

  • 产业类别

    Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

  • 工作内容

    This role will lead the DV team through all project phases—from planning to execution. The incumbent will have strong technical background while leading the team. The responsibilities cover verifying the functional correctness, performance, and robustness of the design.

    Key Responsibilities
    • Develop and execute comprehensive pre-silicon validation test plans
    • Create UVM/RTL-based testbenches
    • Perform simulation, code coverage analysis, and debug failures using tools such as VCS, Questa, or Xcelium.
    • Support assertion-based verification, formal verification, or hybrid methods where applicable.

资格

  • 应征条件

    • Bachelor or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
    • At least 8 years of experience in SoC/NoC design validation, preferably in a product environment.
    • Experience in SystemVerilog, UVM, scripting (Python/Perl/TCL), and simulation tools.
    • Strong debugging and problem-solving skills in a multi-disciplinary team.

  • 英文

    -

  • 其他语言

    English

附加信息

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