Chip Layout Project LeadID:57870
8,000 MYR ~ 9,000 MYRKota Damansara/Petaling Jaya约9小时 ago概述
薪资
8,000 MYR ~ 9,000 MYR
产业类别
Manufacturing(Electronics/Semiconductors)
工作内容
【Job Responsibilities】
• Participate in sub-blocks and module-blocks floor planning and routing from scratch.
• Perform layout blocks verification with sign-off in area (such as DRC, LVS, ANT, ERC & PERC) and troubleshooting the results.
• Good hands-on experience in analog layout device matching techniques, high speed shielding and validation, as well to have acquired broader knowledge in handling high voltage devices.
• Co-work with architect, design lead, designers, layout lead and layout engineers to achieve modules/full chip integration, place and route, chip level verification and tape-out.
• Responsible for layout optimization, post layout extraction and parasitic analysis by ensuring analog and mixed signals circuits meet chip level tape-out, sign-off at desired area, performance, and power.
• Specific technical expertise is desired in a broad range of process technologies from Bipolar, CMOS, DMOS (BCD) to FinFET advance node in complex, high-performance analog and mixed signals circuits layout.
• Proactively look for continuous improvement opportunities in the complete layout flow methodologies (flow, layout, and design) as well as develop accurate IC layout design schedules and resource estimates.
资格
应征条件
• Bachelor's or Master's degree in Electrical / Electronic Engineering or related field (CGPA 3.50 & above).
• Minimum 7 years of experience in chip layout.
• Candidate with full process of chip layout.
• Have managerial and guiding experience.
• Strong problem-solving and analytical skills.
• Good communication and teamwork skills.英文
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其他语言
Mandarin, English
附加信息
福利制度
- Annual Leave
- Medical Leave
- EPF
- SOCSO
- Performance Bonus (subject to personal performance)
- Salary increment (subject to yearly appraisal)
- Employee share (in discount price)
- Team gathering and activities工作时间
9am ~ 6pm
假日
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职业类别
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