229 Jobs
Production Engineer ID:59703
3,000 MYR ~ 4,500 MYRPeraiJob Description
- Design plans using computer-aided design (CAD) and drafting software, applying engineering and manufacturing techniques. Perform reverse engineering based on prototypes or samples and convert them into detailed technical drawings.- Prepare drawings based on given specifications and calculations created by engineers for manufacture, fabrication, maintenance, or repair of the product and structure.- To estimate total required material for specific thickness & length from drawings & manage cutting layout with optimum use of material/plates.- Develops manufacturing processes by designing and modifying equipment for fabricating, building, assembling, and installing components. - -- Prepares product reports by collecting, analyzing, and summarizing information and trends.- Confirms system and product capabilities by designing feasibility and testing methods; testing properties.- Assures system and product quality by designing testing methods; testing finished - product and system capabilities; confirming fabrication, assembly, and installation processes- To supervise a team of engineers/skill workers/sub-contractors by managing tasks to achieve project completion date while aware of maintaining a safe and clean working environment.- Coordinate between production and painter to achieve delivery schedule. Contributes to team effort by accomplishing related results as needed.- Control and submit design appraisal to maintain the validity.- Promote ISO 9001, other relevant quality, product standard and certification maintained by Company.
Benefit
- AL: Starting from 14 days
- MC; Starting from 14 days
- Transport Allowances
- Performances Bonus
- Annual increment
- Medical benefits
- Public HolidaySenior Standard Cell Design EngineerID:59656
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Library Design Engineer to own the end-to-end development of a production-grade standard cell library on leading-edge process nodes. You will drive transistor-level design, multi-Vt cell topology, full characterization, and PPA validation delivering robust, sign-off-ready library views to downstream implementation flows. Seniority level to be determined by experience.Key Responsibilities• Design, simulate, and analyze standard cell circuits at transistor level, including combinational, sequential, clock, and physical utility cells across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths.• Perform layout process-node-shift; guide layout clean-up effort and review for DRC/LVS compliance, EM/IR rules, and parasitic awareness at the cell level.• Define & execute characterization flow to generate complete library views & models, covering timing (NLDM/CCS/ECSM), power (dynamic, leakage, internal), noise, and variation-aware models (LVF/SOCV/POCV); ensure Liberty, LEF, and GDS consistency.• Define & execute QA regression to check library quality; validate cell robustness including noise margin, drive strength, X-propagation, and scan/DFT cell correctness; drive STA correlation using PrimeTime or Tempus to confirm model accuracy in real PD flows.• Lead standard cell library IP integration into Testchip, including Testchip circuit and test plan development; support hardware bring-up and debug.• Perform pre/post-silicon correlation & model/design optimization; drive root-cause analysis for first-silicon issues and implement yield/robustness improvements.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Analog Circuit Design Engineer (Clocking)ID:59653
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in Clocking as described below. Seniority level to be determined by experience.Key Responsibilities• Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted).• Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting.• Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques.• DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Analog Circuit Design Engineer (High-Speed I/O)ID:59652
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in High-Speed I/O as described below. Seniority level to be determined by experience.Key Responsibilities• Design TX/RX, analog front-end, serializers/deserializers, high-speed level shifters, predrivers/drivers, and termination/impedance calibration blocks.• Equalization: Feed-Forward Equalization (FFE), DFE, CTLE and related adaptation/control loops.• Clocking support for links (e.g., CDR interactions, low-jitter clock generation/distribution as needed by PHY).• SI analysis and creation/validation of IBIS/IBIS-AMI models; channel characterization (insertion loss, return loss, crosstalk) and eye diagram margin assessment.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Support interface integration and sign-off: PPA optimization, reliability checks (e.g., EM/IR, aging/overstress), and timing closure collaboration.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Analog Circuit Design Engineer (Pure Analog)ID:59651
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. Seniority level to be determined by experience.Key Responsibilities• Reference generation: bandgap, bias circuits, reference voltages/currents; high-accuracy, low-noise design techniques.• Low offset / low-noise voltage regulators (LDO) and stability/compensation networks; PSRR and transient response optimization.• Voltage and power monitoring circuits: droop detection, voltage detectors, PowerGood and POR generation, analog sensing, and housekeeping blocks.• Power-management components, linear and/or switching-adjacent blocks, charge pumps, as applicable to the SoC/PHY environment.• Design/support ADC/DAC blocks and associated analog support circuits (sampling, references, amplifiers/comparators, clocking).• Voltage and temperature sensor design and characterization. Bandgap and PTAT-based temperature sensing; process corner detection circuits. Sensor readout, digitization, and calibration techniques.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment【Japanese Speaker】QA QC Engineer (Rubber Contact Dept)ID:59623
4,300 MYR ~ 4,800 MYRShah AlamJob Description
1) Coordinate and investigate customer complaints and quality claims.2) Conduct root cause analysis and prepare reports such as 8D reports.3) Coordinate with production and related departments to identify corrective and preventive actions.4) Extract and interpret product requirements from specifications, drawings and technical documents.5) Support internal and external quality audits.
Benefit
Salary: RM 4,300 - 4,800 (depending on working experiences)
(Basic Salary: RM3,500 - 4,000)
- RM 800 (Language allowance) will be provided with N2 or above certificate
※This will be assessed and decided by the client during the interview.
- AL/YEAR: Less than 2y of svc = 8 days, 2y- 5y of svc = 12, more than 5y svc = 16days
- MC/YEAR: Less than 2y of svc = 14 days, 2y- 5y of svc = 18, more than 5y svc = 22 days
- EPF,SOCSO,EIS
- Medical Allowance
- Insurance
- Commuting expenses covered
- Health check
- Housing / Car Subsidy Shceme【Japanese Speaker】 Automation Engineer (Office Automation dept)ID:59621
4,300 MYR ~ 4,800 MYRShah AlamJob Description
1) Auto Inspection handling (programming, teaching and trouble shoot)2) Window person with KD (sister company at ShenZhen, China); cross technology transfer (quality)3) Automation creative4) New models development
Benefit
- Working Time: Mon - Fri : 8:00-17:30
- AL/YEAR: Less than 2y of svc = 8 days, 2y- 5y of svc = 12, more than 5y svc = 16days
- MC/YEAR: Less than 2y of svc = 14 days, 2y- 5y of svc = 18, more than 5y svc = 22 days
- EPF,SOCSO,EIS
- Medical Allowance
- Insurance
- Commuting expenses covered
- Health check
- Housing / Car Subsidy ShcemeProject ManagerID:59617
8,000 MYR ~ 10,000 MYRSeri PetalingJob Description
• Manage the planning, organizing and implementation of complex strategic project/initiatives• Monitor of Project Implementation Plan of overall works• Review progress against plans, reporting progress and result to the Management• Lead and coordinate project team to eliminate the obstacle as well as mentoring the team to improve project approach, process and implementation• Develop and monitoring project plan and track project milestones with appropriate process to ensure the project runs according to schedule and budget• Planning work program of project and monitoring stage completion• Monitoring inspections and test are carried out in accordance to the contract specification• Coordinate, review and submission of progress payment to the customer and facilitate timely certification of sub-contractor claims• To liaise with Client• Co-ordinate interfacing activities works of various sub-contractors• Perform other duties as assigned from time to time
Benefit
1) Annual Leave
(<2 years @ 14 days)
(2-5 years @ 17 days)
(>5 years @ 20 days)
2) Medical Leave
(<2 years @ 14 days)
(2-5 years @ 18 days)
(>5 years @ 22 days)
3) Medical Claims (RM800/year) at panel clinic
4) Dental claim (RM300/year)
5) Insurance (after confirmation)
6) Mobile Phone claim (up to RM120)
7) Mileage, parking & toll claim – for site visit/meeting clientService EngineerID:59476
3,000 MYR ~ 6,000 MYRKota Damansara/Petaling JayaJob Description
Key Responsibilities:- Travel to client sites in Malaysia and ASEAN for machine installation, maintenance, troubleshooting, and repairs.- Provide technical support and training to client machine operators.- Diagnose mechanical/electrical issues and ensure machines run efficiently.- Prepare service reports and maintain accurate documentation.- Work closely with the engineering team to escalate complex issues.
Benefit
- AL: Starting from 10 days
- MC: Starting from 14 days
- PH: 13 days
- EPF, SOCSO
- Parking allowance
- Travel Expenses Claimable
- Medical Claim
- Medical & Personal Accident InsuranceCircuit Design Engineer (Senior/Staff/Principle)ID:59444
6,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
Senior/Staff• Design and implement high speed interfaces and complex mixed-signal circuits using cutting-edge CMOS tech and EDA tools.• Design block IO blocks such as compensation circuit, reference voltage, transmitters and receivers.• Sub blocks include and not confined to , high speed serializers and deserializers, high speed levelshifters , predrivers , drivers , Feed Forward Equalization , DFE , CTLE.• Block to pass rigorous quality and reliability like EM-IR , Aging , Overstress• Run initial SI analysis and IBIS/IBIS-AMI creations.• Timing closure using Prime-Time or equivalent methods.• Work on serial and parallel interfaces.• Work closely with mask designers to deliver the physical design and assist with silicon evaluation.• Perform architecture studies, circuit designs & simulations, floor-planning, instructing mask designers, reliability verifications and silicon bring-up.Principle• Lead and manage team that design and implement high speed interfaces and complex mixed-signal circuits using cutting-edge CMOS tech and EDA tools.• Manage deliveries between function groups for example Layout, RTL , DV , Physical Design and SIPI/Package.• Harmonize schedule and end to end delivery.• Work closely with business development team to understand future projects and resource needed.• First line of clarification and explanation for customer related questions and support.• Work with post silicon team for design intent and required validations.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment