28 Jobs: Job Vacancies for Research & Development(Electrical/Semi-Conductor) Positions
Memory IP Architect / SoC uArchitectID:61253
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan BaruJob Description
Role OverviewWe are seeking a Senior Design Engineer specializing in Network-on-Chip (NoC) to join our cutting-edge semiconductor team. This role involved architecting, designing, and optimizing NoC interconnect solutions for high-performance chips. You will work closely with architects, verification engineers, and software teams to deliver scalable, efficient, and low-latency interconnect designs.Key Responsibilities• NoC Architecture & Design: Develop and optimize high-performance, scalable, and low-latency NoC solutions for SoCs and multi-core processors, components, ensuring performance, area, and power efficiency.• Performance Analysis: Conduct traffic modeling, simulation, and bottleneck analysis to optimize NoC throughput and latency.• Verification & Validation: Collaborate with verification teams to develop testbenches, ensure functional correctness, and debug issues.• Power & Area Optimization: Optimize NoC designs for low-power and area-efficient implementations, working closely with physical design teams.• Integration & Customization: Work on custom NoC configurations, integrating third- party IPs, and tailoring interconnect solutions for specific applications.• Tool & Flow Development: Enhance NoC design methodologies by developing scripts, automation flows, and performance monitoring tools.• Cross-functional Collaboration: Work with chip architects, backend engineers, and software teams to define NoC requirements and optimize for real-world workloads.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementMemory IP Architect / SoC uArchitectID:61252
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan BaruJob Description
We are looking for an experienced Memory IP Architect / uArchitect to lead the architecture and development of next-generation memory solutions for AI, HPC, networking, and custom ASIC applications.This role will drive the definition of memory subsystems, memory controllers, and high-performance SoC memory solutions from concept through silicon.Responsibilities• Define architecture and specifications for Memory IP and SoC subsystems.• Lead memory architecture for DDR5, LPDDR5X/LPDDR6, HBM3E/HBM4, and cache subsystems.• Drive architecture trade-offs across performance, power, area, and cost.• Develop performance models and conduct architecture exploration.• Define memory hierarchy, and system-level optimization strategies.• Collaborate with RTL, DV, DFT, PD, Packaging, Firmware, and Software teams.• Support customer engagements, technical reviews, and roadmap planning.• Guide implementation through silicon bring-up and performance tuning.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementRTL Design Engineer (Junior/Senior)ID:61251
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan BaruJob Description
Position OverviewWe are seeking RTL Design Engineers at Junior/Intermediate and Senior levels to join our Hardware Engineering team, focusing on ASIC and SoC design.The successful candidates will be responsible for RTL development, functional verification, simulation, debugging and design quality throughout the front-end design flow. Depending on experience and seniority, the role will involve implementing well-defined RTL blocks under guidance or independently owning RTL blocks from specification through verification closure and sign-off.Key ResponsibilitiesA. RTL Design & Development- Develop synthesizable RTL using Verilog and/or SystemVerilog in accordance with design specifications and team coding guidelines.- Implement and maintain RTL blocks for ASIC and SoC designs, ensuring functionality, code quality and design efficiency.- Apply synchronous design principles, including clocking, reset strategies, data valid/ready handshaking and clock domain crossing (CDC) techniques.- Design and maintain functional blocks such as finite state machines (FSMs), FIFOs, arbiters, register files, control logic and data paths.- Work with standard bus protocols, including APB and AHB-Lite, with awareness of AXI4.- Consider area, power and performance (PPA) implications when developing and optimizing RTL.- Collaborate with design, verification, physical design (PD), DFT and other cross-functional teams to resolve design issues and improve implementation quality.Junior / Intermediate Level- Implement well-defined RTL blocks based on detailed microarchitecture specifications under the guidance of senior engineers or technical leads.- Develop foundational knowledge of RTL design methodologies, synthesis implications, CDC concepts and low-power design techniques.- Participate in design reviews, identify potential corner cases and proactively raise technical questions or design concerns.- Improve RTL quality and design efficiency based on code review feedback.Senior Level- Independently own RTL blocks from specification review and design implementation through verification closure and sign-off.- Contribute to microarchitecture definition, design specification documentation and technical design reviews.- Optimize RTL for timing closure, area and power through techniques such as pipelining, retiming and appropriate coding strategies.- Implement and evaluate low-power design techniques, including clock gating, isolation cells and retention flops.- Resolve complex RTL design issues and work with physical design teams to address timing and place-and-route feedback.- Provide technical guidance and informal mentoring to junior engineers.B. Functional Verification & Simulation- Develop and execute directed and self-checking SystemVerilog testbenches to verify RTL functionality.- Run simulations, debug functional failures and analyze waveforms using industry-standard tools.- Write SystemVerilog Assertions (SVA) to capture design intent and verify key interface requirements.- Apply functional coverage concepts to assess verification completeness and identify potential coverage gaps.- Collaborate with design verification engineers to investigate issues and ensure design quality.Junior / Intermediate Level- Develop directed testbenches for assigned RTL blocks and execute simulations using tools such as Synopsys VCS, Questa or Icarus Verilog.- Perform waveform debugging using Verdi, DVE or equivalent tools.- Demonstrate basic understanding of UVM concepts, including agents, sequences and scoreboards.- Add basic functional coverage points and develop familiarity with assertions and verification methodologies.Senior Level- Develop and debug more comprehensive testbenches and contribute to UVM agents, sequences and verification environments.- Interpret coverage reports and drive functional coverage closure in collaboration with verification teams.- Apply assertions, assumptions and cover properties, with exposure to formal verification methodologies.- Investigate complex simulation failures and contribute to root-cause analysis across RTL, verification and integration issues.C. Design Quality, Sign-Off & Integration- Ensure RTL designs comply with applicable design specifications, coding standards and quality requirements.- Review simulation results, lint reports and timing information to identify and resolve potential design issues.- Understand the impact of RTL changes on synthesis, timing, integration and downstream implementation.- Collaborate with verification, DFT and physical design teams throughout the design lifecycle.Junior / Intermediate Level- Develop an understanding of static timing analysis (STA), including setup and hold violations.- Resolve common lint warnings and develop familiarity with CDC analysis and synchronizer insertion.- Understand basic DFT concepts, including scan chains and test modes.- Support design reviews and sign-off activities under senior engineer guidance.Senior Level- Interpret STA reports, timing slack and critical paths, and implement RTL changes to address timing issues.- Resolve common CDC and reset domain crossing (RDC) violations and lint issues.- Apply DFT awareness when designing RTL and supporting scan insertion and test mode requirements.- Work closely with physical design teams to resolve implementation-related issues and support design sign-off.- Take ownership of RTL quality and verification closure for assigned blocks.D. Scripting, Automation & Design Tools- Use scripting languages and automation tools to improve design, simulation and debugging efficiency.- Work with existing simulation flows, tool scripts, file lists and build configurations.- Analyze simulation logs and support the maintenance of design and verification workflows.Junior / Intermediate Level- Write basic Python, Tcl or shell scripts to automate repetitive simulation tasks.- Edit existing Makefiles and Tcl run scripts and parse simulation logs.- Demonstrate proficiency in at least one industry-standard simulation tool.Senior Level- Develop and maintain Python, Tcl or shell scripts for simulation automation, regression execution and log analysis.- Manage file lists, hierarchy extraction and simulation flow configurations.- Troubleshoot tool-flow issues and improve automation efficiency where appropriate.- Utilize synthesis and formal verification tools as required by the project.E. Technical Collaboration & Continuous Improvement- Collaborate with cross-functional engineering teams to support successful ASIC/SoC design implementation.- Participate in design reviews, technical discussions and knowledge-sharing activities.- Maintain clear design documentation and communicate technical issues, progress and blockers effectively.- Continuously improve technical knowledge of RTL design, verification methodologies and EDA tools.Junior / Intermediate Level- Work collaboratively within an established design team, seek clarification when requirements are unclear and incorporate feedback from senior engineers.- Provide timely progress updates and proactively communicate design issues or blockers.Senior Level- Drive technical discussions for assigned RTL blocks and document design decisions and implementation considerations.- Coordinate closely with design verification, DFT, physical design and software teams to resolve technical issues.- Mentor junior engineers and contribute to improving team design practices.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementEmulation and Prototyping Engineer (Senior/Lead)ID:61003
10,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking an experienced Emulation & Prototyping Manager to lead the emulation team supporting IP, SoC, and system-level development programs. The role is responsible for defining emulation strategies, managing project execution, developing engineering talent, and driving successful pre-silicon validation and software enablement using industry-leading emulation and prototyping platforms.Key Responsibilities1. Team & People Leadership• Lead, mentor, and grow a high-performing emulation/prototyping team.• Manage resource planning, staffing, performance management, and career development.• Establish engineering best practices, methodologies, and continuous improvement initiatives.2. Technical Leadership• Define and drive emulation/prototyping strategies for IP and SoC programs.• Provide technical guidance on platform architecture, RTL partitioning, acceleration methodologies, and debug.• Evaluate and deploy industry-leading emulation/prototyping technologies and infrastructure.3. Project Delivery• Drive execution of multiple emulation projects to meet quality, schedule, and budget objectives.• Manage project planning, effort estimation, risk assessment, and resource allocation.• Track project progress and provide regular status updates to management and stakeholders.4. Cross-Functional Collaboration• Partner with architects, RTL, DV, firmware, and software teams to enable pre-silicon validation and software bring-up.• Work closely with customers, partners, and EDA vendors to support project and business objectives.• Promote reuse, automation, and standardization across engineering teams.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Design Engineer ID:60688
3,000 MYR ~ 5,500 MYRSepangJob Description
1. Designing• To assist in providing residential, commercial & industrial PV system design services, which include detailed site visit, value engineering based on pre-project proposals, preliminary engineering design preparation, which includes presentation & submission of design in project execution.• To assist the project department & team members in preparing design summary, site survey report, design calculation, bill of quantity, shop/construction drawings, as-built drawings, and other related project technical documents for submission to customers & approvals. • To assist the project department & team members in providing technical support for any design & QC related project submission• To use PV simulation software (Helioscope, PVSyst, etc) and modelling software (SketchUp, AutoCAD, etc) to produce PV system simulation & drawings• To liaise with multiple parties, both internally (interdepartmental) & externally (clients) to ensure that all design & QC aspects in a project is well managed2. Quality Control• To ensure overall design proposal evaluation and compliance to local & international standards, regulations, and requirements.• To conduct regular inspection to ensure that the project execution is in accordance with the design proposal and the system is able to perform as per design. This also includes external inspection (Factory Acceptance Test) from suppliers and other related inspection activities• To conduct proper testing & commissioning in accordance to the local & international standards, regulations and requirements and prepare the necessary documentation & report3. Ad Hoc General• To provide assistance to the Project Manager/COO in day-to-day technical operations
Benefit
- Annual Leaves
- Medical Leaves
- Car Allowance (Subject)
- Phone Allowance (Subject)
- Petrol Claim
- Toll Claim
- Project Expenses Claim
- Medical Claim
- BonusDesign Manager (Semiconductor)ID:60649
10,000 MYR ~ 20,000 MYRBayan LepasJob Description
- Lead and coordinate the project engineering team for project design from programming to IFC design.- Organize routine client and internal engineering team coordination meetings, develop meeting minutes, track ARs, and monitor close-out activities.- Ensure overall project design work follows the company's project execution standards, client requirements and specifications, local compulsory codes, and other applicable regulations.- Organize internal and client project design reviews, and track and monitor the close-out of review comments.- Coordinate and manage discipline/work package interfaces.- Maintain project design change procedures, develop design change logs, and track design changes.- Monitor the overall project design schedule and implement mitigation actions when necessary.- Coordinate with other project stakeholders.- Perform other project design coordination and management tasks.
Benefit
- Annual Leave starting from 8 days
- Medical Leave starting from 14 days
- Transport Allowance
- Meal Allowance
- Medical Benefits
- Performance Bonus
- Yearly IncrementLead Electrical Engineer (Semiconductor)ID:60632
10,000 MYR ~ 20,000 MYRBayan LepasJob Description
• Responsible for overall power supply and distribution system calculation and design according to project and client specifications, and national codes, including but limited to High-Voltage and Low-Voltage system, lighting, lightning system and fire protection electrical system, etc.• Responsible for concept electrical design research in the early project phase; formulating viable electrical design schemes in accordance with the client requirements and relevant specifications, conducting client communication reporting as well as overseeing the consolidation, analysis, and synthesis of electrical demand information• Lead the selection of electrical equipment, and compile detailed equipment technical parameters and specifications• Assist the purchasing department in equipment procurement, review suppliers' technical data, and participate in technical clarification• Leading and coordinating discipline interface• System shop drawing review & approve, technical submittal review & approval• Project site construction schedule, quality and safety coordination
Benefit
- Annual Leave starting from 8 days
- Medical Leave starting from 14 days
- Transport Allowance
- Meal Allowance
- Medical Benefits
- Performance Bonus
- Yearly IncrementLead Mechanical Engineer (Semiconductor)ID:60631
8,000 MYR ~ 15,000 MYRBayan LepasJob Description
• Responsible for the overall calculation and design of mechanical systems in accordance with project requirements, client specifications, and applicable national codes.• Lead the team in completing detailed mechanical design, reviewing design drawings and technical parameters, and resolving key technical issues during the design process.• Track emerging mechanical engineering technologies, promote design optimization and technological applications, and improve system efficiency while reducing energy consumption and operating costs.• Lead and coordinate mechanical discipline interfaces with other engineering disciplines.• Review and approve mechanical system shop drawings and technical submittals.• Coordinate project site construction schedules, quality, and safety.• Participate in preparing technical proposals for project bidding, provide professional technical support, and assist the business team in project negotiations.
Benefit
- Annual Leave starting from 8 days
- Medical Leave starting from 14 days
- Transport Allowance
- Meal Allowance
- Medical Benefits
- Performance Bonus
- Yearly IncrementDFT Logic Design Engineer (Senior/Staff)ID:60263
8,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
Job SummaryWe are seeking an experienced Senior/Staff DFT Logic Design Engineer to support the company's ASIC, SoC, and IP development initiatives in the area of Design for Testability (DFT). The engineer will be responsible for defining DFT architecture, implementing and verifying DFT features, integrating scan and BIST structures at the RTL level, and driving fault coverage from design through silicon bring-up. The role involves close collaboration with RTL, Verification, Physical Design, and Test Engineering teams to deliver high-quality DFT implementation for digital IP and ASIC products.Key Responsibilities1. DFT Architecture & Planning• Define and own the DFT architecture for digital IP and ASIC projects, including scan insertion strategy, compression ratios, JTAG/IEEE 1149.1 boundary scan, MBIST/LBIST planning, and DFT microarchitecture.• Document and maintain DFT specifications throughout the design cycle.• Lead the planning and execution of various DFT feature implementation and verification.2. DFT RTL Design & Integration• Develop and integrate DFT RTL (SystemVerilog/Verilog), including scan wrappers, scan controllers, BIST controllers, test access ports (TAP), and clock/reset control logic.• Implement Memory BIST logic insertion, integration, and verification for IP and ASIC projects.• Ensure DFT structures are synthesis-clean, timing-closed, and do not impact functional performance or power.3. Scan, ATPG & Verification• Implement scan architecture including scan chain stitching, scan controller generation, test compression, and scan timing closure.• Run ATPG to generate and validate stuck-at, transition, path-delay, and cell-aware fault pattern sets.• Perform gate-level simulation (GLS) to verify scan design.• Generate DFT collateral including MBIST patterns, ATPG patterns, scan constraints, timing constraints, BSDL files, and related documentation.• Achieve and sign off target fault coverage metrics.4. Design Quality & Validation• Collaborate with RTL designers to establish DFT-aware coding guidelines.• Perform DFT rule checking, CDC analysis, Lint, and static quality checks to identify and resolve testability violations early in the design cycle.• Support netlist validation through LEC and STA during implementation and timing closure.• Resolve DFT-related ECOs prior to tape-out.5. JTAG & Boundary Scan• Design and verify TAP controllers.• Implement and verify JTAG/Boundary Scan architecture at IP and SoC level.• Generate BSDL files and support Boundary Scan verification.6. Post-Silicon & Manufacturing Support• Support post-silicon validation, silicon power-on, ATE bring-up, and high-volume manufacturing testing.• Work with test engineers to debug ATPG patterns, analyze yield data, and identify root causes related to RTL or physical design issues.• Support test pattern bring-up and production test activities.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementPhysical Design Lead EngineerID:60207
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Physical Design Lead to own and drive the end-to-end physical implementation of testchips and high-speed interface subsystems such as DDR/LPDDR PHY, HBM PHY, and UCIe from netlist through tape-out-ready GDSII on leading-edge process nodes. This is a technical lead role: candidate is expected to take full ownership of implementation scope, mentor junior PD engineers, define methodology, and drive cross-functional coordination with RTL design, DFT, analog/custom layout, and verification teams. Seniority level to be determined by experience.Key Responsibilities• Own end-to-end physical implementation of assigned testchip or high-speed interface subsystem (DDR/LPDDR, HBM, UCIe, or equivalent): floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and chip finishing through to GDSII stream-out.• Coordinate timing closure across all functional modes and PVT corners with the dedicated full-chip STA owner; provide timing-aware physical implementation decisions, flag routing and placement contributors to timing degradation, and execute physical ECOs as directed.• Lead chip-level or subsystem-level floorplan definition: partition boundaries, I/O ring assembly, hard IP (PHY, memory, custom analog) placement, power domain planning, and bump/pad assignment; balance area, routability, and signal-integrity constraints.• Define and enforce the physical design methodology and flow for the team: synthesis-to-P&R handoff conventions, ECO management, signoff checklists, and documentation standards; develop and maintain flow automation scripts for regression, reporting, and incremental ECO runs.• Drive power integrity sign-off: static and dynamic IR-drop analysis (Redhawk/Voltus or equivalent), EM rule compliance, power strapping strategy, and decap insertion; collaborate with circuit and layout teams to resolve violations.• Coordinate physical verification closure (DRC/LVS/ERC/Antenna) using Calibre or equivalent, including custom analog and mixed-signal IP integration; manage foundry rule deck updates and waiver documentation.• Interface with RTL designers, DFT engineers, and analog/custom layout engineers to align on design constraints, resolve integration issues, and ensure clean handoff at each project milestone; represent physical design in architecture and tapeout readiness reviews.• Mentor and technically guide junior and mid-level physical design engineers; review their floorplans and closure strategies; provide actionable feedback and escalate risks proactively to the program lead.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment