29 Jobs: Job Vacancies for Research & Development(Electrical/Semi-Conductor) Positions
Senior Design Engineer ID:60688
3,000 MYR ~ 5,500 MYRSepangJob Description
1. Designing• To assist in providing residential, commercial & industrial PV system design services, which include detailed site visit, value engineering based on pre-project proposals, preliminary engineering design preparation, which includes presentation & submission of design in project execution.• To assist the project department & team members in preparing design summary, site survey report, design calculation, bill of quantity, shop/construction drawings, as-built drawings, and other related project technical documents for submission to customers & approvals. • To assist the project department & team members in providing technical support for any design & QC related project submission• To use PV simulation software (Helioscope, PVSyst, etc) and modelling software (SketchUp, AutoCAD, etc) to produce PV system simulation & drawings• To liaise with multiple parties, both internally (interdepartmental) & externally (clients) to ensure that all design & QC aspects in a project is well managed2. Quality Control• To ensure overall design proposal evaluation and compliance to local & international standards, regulations, and requirements.• To conduct regular inspection to ensure that the project execution is in accordance with the design proposal and the system is able to perform as per design. This also includes external inspection (Factory Acceptance Test) from suppliers and other related inspection activities• To conduct proper testing & commissioning in accordance to the local & international standards, regulations and requirements and prepare the necessary documentation & report3. Ad Hoc General• To provide assistance to the Project Manager/COO in day-to-day technical operations
Benefit
- Annual Leaves
- Medical Leaves
- Car Allowance (Subject)
- Phone Allowance (Subject)
- Petrol Claim
- Toll Claim
- Project Expenses Claim
- Medical Claim
- BonusCMM SpecialistID:60660
2,500 MYR ~ 4,500 MYRKlangJob Description
【Job Summary】We are a leading precision manufacturing specialist providing high-quality plastic injection molding components to top-tier global automotive and industrial partners. Operating from our state-of-the-art production hub in Port Klang, Selangor, our facility integrates advanced tooling, automated molding machinery, and high-precision metrology technologies. To support our rapid expansion and operational excellence, we are actively searching for a hands-on, highly skilled CMM Specialist to join our internal Quality Assurance and Quality Control (QA/QC) team on an urgent basis.In this mission-critical role, you will act as the technical cornerstone of our metrology operations, effectively serving as the vital bridge connecting Metrology, Production, and Engineering departments. Your primary objective will be to drive overall product quality across all lifecycle stages—from initial prototype evaluations and New Product Development (NPD) to volume mass production. You will be directly responsible for writing, testing, and optimizing offline and online Coordinate Measuring Machine (CMM) measurement programs based on complex 2D engineering drawings and 3D CAD models. By interpreting precise Geometric Dimensioning and Tolerancing (GD&T) specifications, you will ensure every component leaving our shop floor meets strict international automotive standards.Beyond standalone measurement, this position requires an agile, collaborative individual who thrives in a fast-paced manufacturing setting. You will work side-by-side with line inspectors and process engineers to resolve shop-floor quality issues rapidly. During new mold trials and product launches, your expert measurement feedback will guide tooling modifications and process optimizations. Furthermore, you will take ownership of the QA laboratory's physical assets, overseeing the routine maintenance, calibration schedules, and precision checks for CMM units and auxiliary measuring equipment.If you bring a proven track record of independent CMM programming capability, a strong foundation in plastic injection molding quality control, and the dynamic energy to hit the ground running from Day 1, this opportunity will offer you a platform to shine, grow, and make a tangible impact on world-class manufacturing projects.【Key Responsibilities】・CMM Programming & Metrology: Write, test, and optimize offline/online CMM programs using CAD models or 2D/3D engineering drawings to verify critical dimensions and specifications accurately.・Daily Production Support: Collaborate closely with the Production and QA/QC teams on key daily quality checks (In-process, Outgoing Inspection) and sample inspections.・New Product Development (NPD): Work side-by-side with Engineering during trial runs, sample verifications, and technical evaluations for new molds and parts.・Equipment Calibration & Care: Ensure proper maintenance, calibration schedules, and routine checks for all CMM machines and precision tools in the QA laboratory.・Internal Root Cause Analysis: Assist cross-functional teams in identifying defect root causes using quality tools (5-Why, Fishbone Diagram) and implement corrective actions.
Benefit
Salary Range: RM2500 – RM4500 (depend on Experience & Skill)
EPF/SOCSO
Insurance (Tokio Marine)
Medical claim (panel clinic)
Bonus (average 3-6 months)
Increment (Every Year)
Uniform
AL 10 days/ MC 14 days
Transport allowance(depends on area : RM100 - below 10km @ RM200 - 11km above.)Design Manager / Design CoordinatorID:60649
10,000 MYR ~ 20,000 MYRBayan LepasJob Description
- Lead and coordinate the project engineering team for project design from programming to IFC design.- Organize routine client and internal engineering team coordination meetings, develop meeting minutes, track ARs, and monitor close-out activities.- Ensure overall project design work follows the company's project execution standards, client requirements and specifications, local compulsory codes, and other applicable regulations.- Organize internal and client project design reviews, and track and monitor the close-out of review comments.- Coordinate and manage discipline/work package interfaces.- Maintain project design change procedures, develop design change logs, and track design changes.- Monitor the overall project design schedule and implement mitigation actions when necessary.- Coordinate with other project stakeholders.- Perform other project design coordination and management tasks.
Benefit
- Annual Leave starting from 8 days
- Medical Leave starting from 14 days
- Transport Allowance
- Meal Allowance
- Medical Benefits
- Performance Bonus
- Yearly IncrementLead Electrical EngineerID:60632
10,000 MYR ~ 20,000 MYRBayan LepasJob Description
• Responsible for overall power supply and distribution system calculation and design according to project and client specifications, and national codes, including but limited to High-Voltage and Low-Voltage system, lighting, lightning system and fire protection electrical system, etc.• Responsible for concept electrical design research in the early project phase; formulating viable electrical design schemes in accordance with the client requirements and relevant specifications, conducting client communication reporting as well as overseeing the consolidation, analysis, and synthesis of electrical demand information• Lead the selection of electrical equipment, and compile detailed equipment technical parameters and specifications• Assist the purchasing department in equipment procurement, review suppliers' technical data, and participate in technical clarification• Leading and coordinating discipline interface• System shop drawing review & approve, technical submittal review & approval• Project site construction schedule, quality and safety coordination
Benefit
- Annual Leave starting from 8 days
- Medical Leave starting from 14 days
- Transport Allowance
- Meal Allowance
- Medical Benefits
- Performance Bonus
- Yearly IncrementLead Mechanical Engineer (HVAC)ID:60631
8,000 MYR ~ 13,000 MYRBayan LepasJob Description
• Responsible for the overall calculation and design of HVAC systems in accordance with project requirements and client specifications and national codes, including but not limited to air-conditioning system, de-smoke systems and process exhaust systems, etc. • Lead the team to complete the detailed design of HVAC systems, review design drawings, technical parameters, and solve key technical problems in the design process• Track cutting-edge HVAC technologies in the industry, promote technology optimization and application, and reduce project energy consumption and operation costs• Leading and coordinating discipline interface• System shop drawing review & approval, technical submittal review & approval• Project site construction schedule, quality and safety coordination• Participate in the preparation of technical proposals for project bidding, provide professional technical support, and assist the business team in project negotiation
Benefit
- Annual Leave starting from 8 days
- Medical Leave starting from 14 days
- Transport Allowance
- Meal Allowance
- Medical Benefits
- Performance Bonus
- Yearly IncrementTool Design Engineer (Stamping)ID:60454
4,500 MYR ~ 5,500 MYRBukit MinyakJob Description
- Provide new material spec., Tooling information, Design checklist, DFMEA.- New tool design layout and drawings.- Participate in new tool assembly and debugging tool.- Involved in improvement project and modification tool with Die Maintenance Department.- To order standard part and follow up delivery lead time according to tooling schedule.- Involve in vendor fabrication quality issue and delivery issue to meet the tooling schedule.- Review of FA report and follow-up on sample submission.- Participate in transfer tooling project for buy off.- To handle other tasks and duties as and when requested by superior.
Benefit
- AL: 12 days, increase gradually based on company policy.
- Individual Insurance
- Medical RM200/year & Dental RM300/year
- Toll claimable (Candidate from Island only)
- Mobile allowances (Depend)
- Individual bonus - 1month fixed
- Increment every year (July) -Rate based on performanceDFT Logic Design Engineer (Senior/Staff)ID:60263
8,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
Job SummaryWe are seeking an experienced Senior/Staff DFT Logic Design Engineer to support the company's ASIC, SoC, and IP development initiatives in the area of Design for Testability (DFT). The engineer will be responsible for defining DFT architecture, implementing and verifying DFT features, integrating scan and BIST structures at the RTL level, and driving fault coverage from design through silicon bring-up. The role involves close collaboration with RTL, Verification, Physical Design, and Test Engineering teams to deliver high-quality DFT implementation for digital IP and ASIC products.Key Responsibilities1. DFT Architecture & Planning• Define and own the DFT architecture for digital IP and ASIC projects, including scan insertion strategy, compression ratios, JTAG/IEEE 1149.1 boundary scan, MBIST/LBIST planning, and DFT microarchitecture.• Document and maintain DFT specifications throughout the design cycle.• Lead the planning and execution of various DFT feature implementation and verification.2. DFT RTL Design & Integration• Develop and integrate DFT RTL (SystemVerilog/Verilog), including scan wrappers, scan controllers, BIST controllers, test access ports (TAP), and clock/reset control logic.• Implement Memory BIST logic insertion, integration, and verification for IP and ASIC projects.• Ensure DFT structures are synthesis-clean, timing-closed, and do not impact functional performance or power.3. Scan, ATPG & Verification• Implement scan architecture including scan chain stitching, scan controller generation, test compression, and scan timing closure.• Run ATPG to generate and validate stuck-at, transition, path-delay, and cell-aware fault pattern sets.• Perform gate-level simulation (GLS) to verify scan design.• Generate DFT collateral including MBIST patterns, ATPG patterns, scan constraints, timing constraints, BSDL files, and related documentation.• Achieve and sign off target fault coverage metrics.4. Design Quality & Validation• Collaborate with RTL designers to establish DFT-aware coding guidelines.• Perform DFT rule checking, CDC analysis, Lint, and static quality checks to identify and resolve testability violations early in the design cycle.• Support netlist validation through LEC and STA during implementation and timing closure.• Resolve DFT-related ECOs prior to tape-out.5. JTAG & Boundary Scan• Design and verify TAP controllers.• Implement and verify JTAG/Boundary Scan architecture at IP and SoC level.• Generate BSDL files and support Boundary Scan verification.6. Post-Silicon & Manufacturing Support• Support post-silicon validation, silicon power-on, ATE bring-up, and high-volume manufacturing testing.• Work with test engineers to debug ATPG patterns, analyze yield data, and identify root causes related to RTL or physical design issues.• Support test pattern bring-up and production test activities.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementPhysical Design Lead EngineerID:60207
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Physical Design Lead to own and drive the end-to-end physical implementation of testchips and high-speed interface subsystems such as DDR/LPDDR PHY, HBM PHY, and UCIe from netlist through tape-out-ready GDSII on leading-edge process nodes. This is a technical lead role: candidate is expected to take full ownership of implementation scope, mentor junior PD engineers, define methodology, and drive cross-functional coordination with RTL design, DFT, analog/custom layout, and verification teams. Seniority level to be determined by experience.Key Responsibilities• Own end-to-end physical implementation of assigned testchip or high-speed interface subsystem (DDR/LPDDR, HBM, UCIe, or equivalent): floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and chip finishing through to GDSII stream-out.• Coordinate timing closure across all functional modes and PVT corners with the dedicated full-chip STA owner; provide timing-aware physical implementation decisions, flag routing and placement contributors to timing degradation, and execute physical ECOs as directed.• Lead chip-level or subsystem-level floorplan definition: partition boundaries, I/O ring assembly, hard IP (PHY, memory, custom analog) placement, power domain planning, and bump/pad assignment; balance area, routability, and signal-integrity constraints.• Define and enforce the physical design methodology and flow for the team: synthesis-to-P&R handoff conventions, ECO management, signoff checklists, and documentation standards; develop and maintain flow automation scripts for regression, reporting, and incremental ECO runs.• Drive power integrity sign-off: static and dynamic IR-drop analysis (Redhawk/Voltus or equivalent), EM rule compliance, power strapping strategy, and decap insertion; collaborate with circuit and layout teams to resolve violations.• Coordinate physical verification closure (DRC/LVS/ERC/Antenna) using Calibre or equivalent, including custom analog and mixed-signal IP integration; manage foundry rule deck updates and waiver documentation.• Interface with RTL designers, DFT engineers, and analog/custom layout engineers to align on design constraints, resolve integration issues, and ensure clean handoff at each project milestone; represent physical design in architecture and tapeout readiness reviews.• Mentor and technically guide junior and mid-level physical design engineers; review their floorplans and closure strategies; provide actionable feedback and escalate risks proactively to the program lead.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementLogic Design Engineer / RTL Design Engineer (Senior/Staff/Principal)ID:60086
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan BaruJob Description
Job SummaryThe Logic Design Engineer will be responsible for the architecture, design, implementation, and delivery of high-performance digital IPs and subsystems for ASIC/SoC products. The role involves microarchitecture definition, RTL development, functional validation support, timing convergence, and IP release activities while collaborating closely with architecture, verification, physical design, firmware, and system teams to achieve performance, power, area (PPA), and quality targets.The engineer will take ownership of IP or subsystem-level RTL implementation from specification through customer release and contribute to design quality through lint, CDC, formal verification, timing closure, and design reviews.Key Responsibilities1. RTL Design & Microarchitecture• Define and implement block-level or subsystem-level RTL architecture based on product specifications.• Develop high-quality RTL using Verilog/SystemVerilog for ASIC/SoC products.• Participate in microarchitecture definition and document design decisions.• Ensure RTL complies with coding standards, synthesis guidelines, and design methodologies.• Review RTL implementation and participate in peer design reviews.2. Digital IP Development• Own assigned digital IPs or logic blocks from specification through implementation and release.• Design high-speed digital logic capable of achieving timing closure on advanced process nodes.• Collaborate with architects, firmware, and system engineers to ensure correct feature implementation.• Support IP integration into subsystem or SoC environments.3. Design Quality & Verification Support• Produce functional test plans covering design requirements.• Support Design Verification teams in debugging simulation failures and functional issues.• Perform and resolve: Lint, CDC/RDC, Formal Equivalence Verification (FEV), Low Power (UPF/CPF)• Participate in coverage closure and verification reviews.4. Timing & Design Closure• Work closely with Physical Design and STA teams to achieve timing closure.• Support synthesis, timing optimization, clock-domain crossing, and low-power implementation.• Develop and validate timing constraints (SDC) and power intent where applicable.• Resolve setup/hold timing issues and support floorplan optimization.5. IP Release & Documentation• Own IP release deliverables including RTL packages, documentation, and quality sign-off.• Prepare design documentation, architecture specifications, and implementation reports.• Ensure all deliverables meet internal quality standards and customer requirements.6. Cross-functional Collaboration• Work closely with Architecture, DV, Physical Design, Firmware, Validation, and System Engineering teams.• Participate in design reviews, technical discussions, and project planning.• Contribute to continuous improvement of RTL design methodology and automation flows.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementMemory Layout LeadID:60085
10,000 MYR ~ 12,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Memory Layout Lead to independently execute physical layout design and completion of SRAM and/or Register File (RF) memory macros. You will own full-custom layout from floorplanning through DRC/LVS sign-off, working closely with circuit designers to deliver pitchmatched, tape-out-ready memory blocks. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom physical layout of SRAM and/or multi-port Register File (RF) macros, including bit cell arrays, periphery circuits (decoders, wordline drivers, sense amplifiers, write drivers), and I/O rings, to tape-out quality with limited guidance.• Interpret circuit schematics and layout specifications to implement pitch-matched arrays and hierarchical peripheral blocks, ensuring correct device sizing, poly/diffusion pitches, and metal routing within process constraints.• Drive DRC, LVS, and ERC verification to closure independently; track and resolve violations systematically and maintain sign-off records for assigned memory blocks.• Perform parasitic extraction (PEX) and work directly with circuit designers on post-layout simulation correlation; flag and resolve layout-induced timing or performance degradations.• Implement design-for-manufacturability (DFM) best practices: critical layer fill, dummy device insertion, metal density compliance, and multi-patterning coloring at advanced nodes.• Produce accurate layout deliverables including GDS stream-out, LEF abstracts, and associated documentation; maintain revision history and design review records.• Interface with circuit designers and physical verification engineers to resolve layout-toschematic mismatches and drive end-to-end closure on all assigned memory macros.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
