24个职位: 招聘信息 研发(工程师(半导体))
Principle Digital Design Engineer (Logic)ID:59118
20,000 MYR ~ 25,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
This role will be responsible for architecting, designing, and verifying complex digital IPs and subsystems for SoCs or ASIC/FPGA-based products. As a senior role, it requires to work closely with system architects, verification, and physical design teams to deliver high-performance, power-efficient, and functionally correct RTL implementations. Overall, the responsibilities cover wider scope encompassing from IP to subsystem level and SOC level global issues.Key ResponsibilitiesArchitect with system engineers to perform:-• Define IP specifications, architecture & test concept.• Specify correct implementation of RTL design and verify digital circuits to deliver high performance, low power, and efficient implementation.• Conduct design reviews and support in documentation.• Support verification engineer to define verification test items.• Support in the roadmap formulation for the sensor IPs.• Support view generation engineers to verify the correctness of the Ips views.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementIP Logic Design Principle EngineerID:58602
20,000 MYR ~ 35,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
The IP Logic Design Principle Engineer will be responsible for architecting microarchitecture design implementation of an IP, spanning across all IP stack such as application layer, transaction layer, link layer, die to die layer, physical layer. Ability to code verilog / system verilog RTL for complex IP, review RTL coding, orchestra IP development phase for projects from beginning to completion. This includes the ability to technically drive the IP team on Design / Validation in completing technical tasks up to IP releases for customers. Candidate must be also capable of solving high speed timing convergence on various processes and collaborate with cross-functional teams to meet project specifications. The role will drive performance optimization and ensuring design functionality through verification and validation processes.Key Responsibilities:1. IP Microarchitecture Definitions• Define microarchitecture definition across layers and define a clean inter unit partition requirements.• Drive design team to deliver best-in-class IP design that optimizes for area, latency, power and performance.• Ability to distribute and drive the design team to implement high quality design and meeting time to market requirements.2. IP Design Responsibility• Implement very complicated high-speed design which can converge timing convergence at high frequency.• Capable of orchestrating the team on right directions of timing convergence, CDC, lintra and etc. for tools closure.3. IP Quality Responsibility• Review IP design and validation testplan to make sure IP Design is at top notch quality.4. IP Releases• Deep knowledge on Lint and CDC flow and ability to drive the Lint and CDC convergence.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementIP Engineering DirectorID:58600
25,000 MYR ~ 40,000 MYRBayan Lepas, Bayan Baru工作内容
Highly skilled and visionary IP Engineering Director, to lead the development and delivery of reusable semiconductor IP that powers advanced SoCs, chiplets, and multi-die solutions. This role requires deep expertise in semiconductor IP design, verification, and integration, combined with proven leadership in building and managing engineering teams. While the position is primarily focused on hardware IP development (digital, analog, or mixed-signal), software development experience—such as firmware, device drivers, or modeling frameworks—is a strong plus, enabling HW/SW co-design, system-level optimization, and accelerated customer adoption. The IP Engineering Director will define technical roadmaps, oversee execution, and collaborate with cross-functional teams to deliver silicon-proven IP solutions that meet aggressive power, performance, and area (PPA) targets.Key Responsibilities1. Leadership & Strategy• Define and execute the company’s IP engineering roadmap aligned with product strategy.• Build and lead a world-class IP engineering team across design, verification, validation, and integration.• Mentor and develop engineering leaders, fostering innovation, collaboration, and technical excellence.• Drive continuous improvement in design methodology, automation, and productivity.2. IP Development & Execution• Lead architecture, micro-architecture, and RTL design of reusable IP (e.g., memory interfaces, high-speed I/Os, interconnects, SerDes, or accelerators).• Oversee verification, validation, and sign-off, ensuring robust, silicon-proven IP delivery.• Collaborate with SoC, package, and system teams for seamless integration into chiplet and multi-die systems.• Support post-silicon debug, bring-up, and customer deployment of IP blocks.3. Cross-Functional Collaboration• Partner with software teams on firmware, drivers, and simulation frameworks to ensure full-stack enablement.• Engage with product, SoC, and system architects to align IP functionality with end-market requirements.• Collaborate with foundries, EDA vendors, and ecosystem partners to enhance IP design flows and deployment.4. Program Management & Delivery• Own IP program planning, milestones, schedules, and risk management.• Ensure timely delivery of high-quality IP to internal design teams and external customers.• Drive design reuse and scalability across multiple projects and product lines.5. Execution & Delivery• Own NoC project planning, execution, and delivery, ensuring schedule adherence and quality.• Establish and improve design methodologies, verification flows, and automation for rapid, reliable development.• Support bring-up, debug, and performance validation in both pre-silicon and post-silicon environments.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementNetwork-on-Chip (NoC) Team Engineering DirectorID:58599
25,000 MYR ~ 40,000 MYRBayan Lepas, Bayan Baru工作内容
This role will lead the architecture, design, and development of high-performance interconnect solutions for SoCs, chiplets, and advanced packaging systems. The ideal candidate will have deep expertise in NoC architecture, RTL/micro-architecture design, performance modeling, and verification, combined with strong leadership skills. Experience in both hardware and software development is a strong plus, as it enables system-level optimization, modeling, and seamless HW/SW co-design for next-generation NoC solutions. The NoC Team Director will drive technical strategy, manage execution, mentor a multidisciplinary team, and collaborate with cross-functional partners to deliver state-of-the-art interconnect IP for data-intensive and AI-driven applications. Key Responsibilities1. Leadership & Strategy• Define and execute the company’s NoC technology roadmap, aligned with product and system- level requirements.• Build, mentor, and lead a high-performing team of architects, designers, verification engineers, and performance modelers.• Foster innovation in NoC design, methodology, and automation to achieve best-in-class power, performance, and area (PPA).2. NoC Architecture & Design• Lead the design of scalable, configurable, and high-bandwidth NoC architectures for heterogeneous SoCs and multi-die systems.• Drive micro-architecture, RTL design, and integration of NoC subsystems, including coherency, QoS, and security features.• Oversee performance modeling, traffic analysis, and system-level simulation to ensure NoC meets latency and bandwidth requirements.• Collaborate with physical design teams to optimize NoC topology, floorplanning, and timing closure. 3. Cross-Functional Collaboration• Partner with CPU/GPU/AI accelerator, memory subsystem, and IP teams to define NoC interfaces and integration requirements.• Collaborate with software teams on NoC modeling frameworks, traffic generators, drivers, and firmware for validation and optimization.• Engage with product and system architects to align NoC capabilities with end-market requirements (AI/ML, datacenter, automotive, mobile).4. Execution & Delivery• Own NoC project planning, execution, and delivery, ensuring schedule adherence and quality.• Establish and improve design methodologies, verification flows, and automation for rapid, reliable development.• Support bring-up, debug, and performance validation in both pre-silicon and post-silicon environments.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
