185个职位: Manager

Sales Manager (SEA) ID:60036
14,000 MYR ~ 16,000 MYRSimpang Ampat
工作内容
• Develops a business plan and sales strategy for the market that ensures attainment of company sales goals and profitability.• Prepares action plans by individuals as well as by team for effective search of sales leads and prospects.• Developing new markets and customers while maintaining key customers.• Responsible for sales team’s performance and business target. Must be able to lead a group of Sales Team.• Provide accurate forecasting of sales opportunities from a scope, timing and revenue perspective.• Plan, develop and manage sales target and strategies and monitor Sales Department activities. • Identify and develop new business opportunities and success retention of existing customers. • Responsible for new market penetration to build networking locally and internationally • To conducts sales presentation and negotiates with customers on quotation • Responsible for the performance of sales department as well as lead the sales team in achieving department & individual sales targets• Prepare and manage bi-weekly, monthly, quarterly and yearly Sales forecast for review by the Management. • To consistently motivate and maintain unity in the team and inter-department at the same time ensuring all member are adequately trained.• To ensure timely collection of payment of customers & ensuring a healthy debtor aging status.• Ensure all customer inquiries and complaints are handled promptly and ability to handle difficult customers professionally.• Responsible to identify the risks and opportunities, evaluate the risks, control the risks and communicate risks and opportunities to all department staff and interested parties. • Other duties and assignments as instructed by superiors from time to time.• To comply to all requirements of ISO (inclusive of all standards approved by the Management) and to adhere to general safety practices, standard operating procedure, work instructions, policies and guidelines provided by the company.
福利制度
Salary range: RM14,000 - RM16,000

Fixed allowances:
• Phone allowance
• Petrol allowance

*Entitled to commission

<Other benefits>
• Contractual bonus (pro-rated based on confirmation date)
• Annual bonus (based on individual and company performance)
• Medical insurance

<If travelling>
• Daily allowance (Depending on the country they visit)
Sales Manager (Packaging Solution)ID:60068
8,000 MYR ~ 10,000 MYRBangsar
工作内容
■ ROLE OVERVIEWAs our first Sales Manager in Malaysia, you will be the driving force behind the China headquarter. This is a strategic role requiring a blend of high-touch account management for our existing global client and aggressive business development to establish our footprint in the Malaysian packaging market.■ KEY RESPONSIBILITIES1. Market Entry & Business Development・Identify and penetrate new market segments in Malaysia (e.g., Food & Beverage, Consumer Electronics, Industrial, or E-commerce).・Develop and execute a comprehensive sales strategy to acquire new local and multinational accounts.・Conduct market research to stay ahead of local packaging trends, competitor pricing, and regulatory requirements.2. Strategic Account Management・Act as the primary local point of contact for our existing key client, ensuring 100% satisfaction and seamless service delivery.・Coordinate with the HQ in China regarding production timelines, customized specifications, and quality control.3. Sales Operations & Leadership・Manage the end-to-end sales process: from initial lead generation and technical consultation to negotiation and closing.・Prepare and present sales forecasts, budget reports, and market feedback to HQ management.・Assist in the setup of the Malaysia sales office operations as the company grows.4. Technical Consultation・Provide expert advice on packaging materials, sustainability options, and cost-effective design solutions tailored to the Malaysian climate and logistics landscape.
福利制度
・Basic Salary = RM 8,000 - RM 10,000
・AL 8d, MC 14d
・Commission & Incentive scheme will be discussed in the interview
・All business expenses are claimable
・Other benefits will be discussed in the interview
General Manager (Japanese Speaker)ID:60102
10,000 MYR ~ 15,000 MYROther Selangor District
工作内容
• Assist MD to oversee overall operation including sales, accounting, HR, purchasing, maintenance and etc.• Communicate with Japan head quarter office for business guidance, instruction and information sharing.• Accountable for the business revenue and the entire business operations in relation to customer continuity.• Enhance operational excellence and delivering absolute customer satisfaction and people development.• Manage overall business operations of company including engineering, supply chain and other support enabling functions such as HR, accounting to strive for optimum business performance and financial contribution.• Answerable to the business owner in term of business improvement.• Support the needs of the operations team for the business operations.• Develop and implement Company’s strategies and business plans.
福利制度
◆　AL
> 14d 2~5y
> 16d >5y
> 21d >10y

◆　Transport allowance, based on distance (one way)
0 km - <5 km: 2.40
5 km - <15 km: 3.20
15 km - <25 km: 4.20
25 km - <35 km: 5.50

◆　Increment upon confirmation – based on individual’s merit.

◆　Annual Increment – based on individual’s merit.

◆　Annual Bonus – based on individual employee’s performance and company’s profit.
Average 1 month, not more than 4 month’s salary based.
＊＊Attendance record will also influence bonus amount. Prorated Bonus for service between 3 months (subject to confirmed in appointment) to less than a year.

◆　Medical coverage of RM1,500 per year, hospitalization case by case.

◆　Group Accidental insurance coverage.

◆　Company trip/outing will be once in every two years depending on employees’ performance and company’s profit

◆　Company eat-out at an interval that varies from year to year depending on employees’ performance and company’s profit.

◆　Liabilities: EPF, SOCSO, EIS
Operation Management, Senior Manager (MD Department) [Japanese Speaker]ID:60103
10,000 MYR ~ 15,000 MYROther Selangor District
工作内容
• Assist MD to oversee overall operation including sales, accounting, HR, purchasing, maintenance and etc.• Communicate with Japan head quarter office for business guidance, instruction and information sharing.• Accountable for the business revenue and the entire business operations in relation to customer continuity.• Enhance operational excellence and delivering absolute customer satisfaction and people development.• Manage overall business operations of company including engineering, supply chain and other support enabling functions such as HR, accounting to strive for optimum business performance and financial contribution.• Answerable to the business owner in term of business improvement.• Support the needs of the operations team for the business operations.• Develop and implement Company’s strategies and business plans.
福利制度
◆　AL
> 14d 2~5y
> 16d >5y
> 21d >10y

◆　Transport allowance, based on distance (one way)
0 km - <5 km: 2.40
5 km - <15 km: 3.20
15 km - <25 km: 4.20
25 km - <35 km: 5.50

◆　Increment upon confirmation – based on individual’s merit.

◆　Annual Increment – based on individual’s merit.

◆　Annual Bonus – based on individual employee’s performance and company’s profit.
Average 1 month, not more than 4 month’s salary based.
＊＊Attendance record will also influence bonus amount. Prorated Bonus for service between 3 months (subject to confirmed in appointment) to less than a year.

◆　Medical coverage of RM1,500 per year, hospitalization case by case.

◆　Group Accidental insurance coverage.

◆　Company trip/outing will be once in every two years depending on employees’ performance and company’s profit

◆　Company eat-out at an interval that varies from year to year depending on employees’ performance and company’s profit.

◆　Liabilities: EPF, SOCSO, EIS & HRDF LEVI (standard requirement)
Memory Layout Designer/LeadID:60085
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru
工作内容
We are seeking a Memory Layout Designer to independently execute physical layout design and completion of SRAM and/or Register File (RF) memory macros. You will own full-custom layout from floorplanning through DRC/LVS sign-off, working closely with circuit designers to deliver pitchmatched, tape-out-ready memory blocks. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom physical layout of SRAM and/or multi-port Register File (RF) macros, including bit cell arrays, periphery circuits (decoders, wordline drivers, sense amplifiers, write drivers), and I/O rings, to tape-out quality with limited guidance.• Interpret circuit schematics and layout specifications to implement pitch-matched arrays and hierarchical peripheral blocks, ensuring correct device sizing, poly/diffusion pitches, and metal routing within process constraints.• Drive DRC, LVS, and ERC verification to closure independently; track and resolve violations systematically and maintain sign-off records for assigned memory blocks.• Perform parasitic extraction (PEX) and work directly with circuit designers on post-layout simulation correlation; flag and resolve layout-induced timing or performance degradations.• Implement design-for-manufacturability (DFM) best practices: critical layer fill, dummy device insertion, metal density compliance, and multi-patterning coloring at advanced nodes.• Produce accurate layout deliverables including GDS stream-out, LEF abstracts, and associated documentation; maintain revision history and design review records.• Interface with circuit designers and physical verification engineers to resolve layout-toschematic mismatches and drive end-to-end closure on all assigned memory macros.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Standard Cells Library Layout Designer/LeadID:60084
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru
工作内容
We are seeking a Standard Cells Library Layout Designer to execute the full-custom physical layout of a production-grade standard cell library on leading-edge process nodes. Working from circuit schematics and cell specifications provided by the design team, you will draw, verify, and deliver DRC/LVS-clean cell layouts across combinational, sequential, clock, and physical utility cell types, contributing to a high-quality, tapeout-ready library with minimal day-to-day supervision. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout for a wide range of standard cells: combinational logic, sequential (flip-flops, latches), clock cells, and physical utility cells, across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths, working to cell specifications and floorplans defined by the lead engineer.• Implement FEOL layers (poly, diffusion, fin/nanosheet, contacts, local interconnect) and BEOL routing (M1–M2, vias) in accordance with foundry design rules, ensuring correct device fingering, pin placement, and power rail connections as specified.• Run DRC and LVS verification using Calibre (or equivalent) after each cell completion; independently identify, debug, and resolve violations to achieve a clean sign-off without requiring senior engineer intervention on routine checks.• Ensure correct cell boundary and abutment compliance: maintain CPP-grid alignment, N-well continuity, dummy poly at boundaries, and power rail stitching so that cells abut cleanly in row-based placement without post-assembly DRC failures.• Review layout against parasitic extraction (PEX) results and collaborate with circuit design engineers to address RC-sensitive nodes; make targeted layout adjustments to meet post-extraction simulation targets.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Custom Layout Designer/LeadID:60083
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru
工作内容
We are seeking an Custom Layout Designer to execute full-custom physical layout of high-performanceanalog/mixed-signal IPs, working from schematic through to tape-out-ready implementation independently andwith limited guidance. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout of analog/mixed-signal IP blocks (bandgap, LDO, PLL, oscillators, I/O, eFUSE, and other Foundation IP blocks) from schematic to tape-out, independently and with limited guidance.• Perform cell-level and block-level floorplanning: power/ground planning, device placement, and routing channel allocation with awareness of signal integrity and parasitic impact on circuit performance.• Apply custom layout best practices: device matching (common-centroid, interdigitation), shielding, guard rings, well taps, and substrate isolation to meet noise, mismatch, latch-up, and reliability requirements.• Run and resolve DRC, LVS, and ERC sign-off using Calibre or equivalent; ensure clean tape-out verification across all required foundry rule decks.• Support or drive parasitic extraction (Calibre xRC or Quantus QRC) and collaborate with the circuit designer to close performance gaps identified in post-layout simulation.• Participate in layout reviews with circuit designers: interpret schematic annotations, critical net callouts, and back-annotate layout-sensitive constraints (e.g., symmetry requirements, shielding needs, critical parasitics).• Manage layout deliverables for assigned IP blocks: track task progress, provide reliable schedule estimates, and flag risks to the design lead proactively.• Maintain organized GDS/OA databases; adhere to layer naming conventions and ensure version-controlled handoff of layout data aligned with IP library delivery standards.• Collaborate with the physical verification team on foundry rule deck updates and process-node-related DRC changes; support layout porting across technology nodes as required.• Meet EM/IR, electrostatic discharge (ESD), and reliability layout rules; adhere to design methodology guidelines and sign-off checklists established for the IP library.• Support testchip integration: contribute layout views for pad ring assembly, coordinate top-level integration with the responsible designer, and assist in post-silicon debug where layout artifacts are suspected.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Design Automation Engineer (Standard Cells Library)ID:60082
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru
工作内容
We are seeking a Standard Cells Library Design Automation Engineer to develop and maintain the characterization flow that supports our standard cell library design team. Working alongside circuit design and layout engineers, you will automate SPICE-to-Liberty characterization runs across PVT corners, execute library QA regressions, and keep the flow reliable and reproducible through every release cycle. This is a hands-on flow-execution role focused on throughput, repeatability, and data quality.Key Responsibilities• Develop, maintain, and execute the standard cell library characterization flow using industry-standard tools (e.g. Cadence Liberate, Synopsys PrimeLib, or equivalent), producing Liberty models across the required PVT corners and Vt flavors.• Automate job submission, corner sweeping, and result collection on compute clusters; monitor runs, triage failures, and re-run incremental jobs efficiently.• Set up and run characterization testbenches and configuration files from cell netlists, .inst definitions, and SPICE models; support the circuit design team by turning around characterization requests on schedule.• Run library QA regressions (Liberty syntax checks, NLDM/CCS consistency, monotonicity, cross-corner sanity) and flag out-of-spec cells back to the design team with clear diagnostic data.• Package and version characterization outputs (.lib, .db) and maintain the release directory structure so that downstream users receive a clean, reproducible drop each cycle.• Write and maintain Python and Tcl scripts for flow glue, report generation, and regression dashboards; keep the flow documentation current.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Design Automation Engineer (Analog/Mixed-Signal IP)ID:60081
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru
工作内容
We are seeking a Design Automation (DA) Engineer to develop, deploy, and maintain EDA flows, scripting infrastructure, and methodology tooling that accelerate the full lifecycle of analog/mixed-signal IP — from schematic capture and simulation through physical verification, characterization, and customer delivery. The DA Engineer works as an embedded enablement partner to circuit and layout designers, translating manual, repetitive, and error-prone tasks into robust, scalable automation. Seniority level to be determined by experience.Key Responsibilities• Develop and maintain simulation automation and regression flows using ADE-XL/Assembler, Spectre, and/or HSPICE; implement corner, Monte Carlo, and mismatch batch runs, compare results against specification limits, and report pass/fail status to designers.• Develop SKILL/SKILL++ and Python scripts to automate repetitive layout operations: parameterized cell (PCell) authoring, constraint-driven routing, DRC-clean template generation, and pre-tapeout LVS/DRC batch checking.• Own and maintain the physical verification flow: Calibre DRC/LVS/xRC, Pegasus/PVS, and/or Quantus QRC extraction; automate rule deck updates following foundry process revisions, and maintain a documented automated waiver management system.• Develop and maintain IP characterization flows; automate Liberty (.lib) timing/power view generation, IBIS model extraction, and datasheet/specification reporting pipelines for customer delivery.• Support PDK qualification and updates: validate simulation model files, verify PCell correctness after foundry PDK revisions, and communicate technology node constraints (layout-dependent effects, advanced-node DRC restrictions) to circuit and layout designers.• Serve as the primary DA support contact for circuit and layout designers: diagnose tool issues, resolve flow bottlenecks, provide training on automation scripts and new methodologies, and continuously improve designer experience based on feedback.• Manage EDA tool installation, licensing, compute cluster job submission, and tool vendor engagement for issue escalation, new tool evaluation, and methodology co-development.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Sr Analog Circuit Design Engineer (Clocking)ID:60080
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong
工作内容
We are seeking an experienced Analog / Mixed-Signal Circuit Design Engineer to develop high-performance High-Speed I/O analog buffer circuits for LPDDR6 memory interfaces, from architecture definition through tapeout and silicon bring-up. The candidate should have strong hands-on expertise in high-speed analog I/O design, with proven ownership of silicon-proven blocks. Seniority level will be determined based on experience.Key Responsibilities• Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits.• Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements.• Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications.• Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off.• Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics.• Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects.• Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control.• Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging).• Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed.• Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment