概述
薪资
3,000 MYR ~ 8,000 MYR
工作行业
Manufacturing(Electronics/Semiconductors)
工作内容
• Develop and maintain material planning strategies to ensure uninterrupted production.
• Analyze demand forecasts and adjust material plans accordingly to avoid shortages or excess inventory.
• Develop and maintain accurate material plans to meet production schedules, ensuring the availability of materials at the right time and in the right quantity.
• Collaborate with internal & external stakeholders such as production planners, SQE and procurement team, to ensure timely material availability & requirements.
• Work closely with logistics and warehouse teams to streamline material shortage and distribution.
• Identify and resolve material shortages, excess stock, and supply chain bottlenecks.
• Generate reports on material status, usage, and planning efficiency for management review.
• Ensure compliance with company policies, quality standards, and industry regulations.
资格
任职资格
<Requirements>
• Min Diploma and Bachelor's Degree holder in Supply Chain Management, Business Administration, Business Studies or related field
• Minimum 3 years of experience in material planning, production planning, supply chain, or inventory control
• Proficient in using SAP Systems
• Proficiency in Microsoft Excel and data analysis
<Advantageous>
• Knowledge of inventory management and procurement processes
• Ability to read engineering drawings or BOMs (Bills of Materials)英文
-
其他语言
Malay, Mandarin, English
附加信息
福利制度
Salary: RM3,000 - RM8,000
AL: Starting from 14 days
MC: 14 / 18 / 22 days
<Other benefits>
• Meal subsidy
• Fixed allowances: Phone, transport
• After confirmation: Medical insurance, health screening, dental/optical (They will share more during interview session)工作时间
08:30 ~ 17:30
假日
Follow Malaysia's PH
职业类别
相关职缺
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8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan Baru职业类别
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工作内容
Role OverviewWe are seeking a Senior Design Engineer specializing in Network-on-Chip (NoC) to join our cutting-edge semiconductor team. This role involved architecting, designing, and optimizing NoC interconnect solutions for high-performance chips. You will work closely with architects, verification engineers, and software teams to deliver scalable, efficient, and low-latency interconnect designs.Key Responsibilities• NoC Architecture & Design: Develop and optimize high-performance, scalable, and low-latency NoC solutions for SoCs and multi-core processors, components, ensuring performance, area, and power efficiency.• Performance Analysis: Conduct traffic modeling, simulation, and bottleneck analysis to optimize NoC throughput and latency.• Verification & Validation: Collaborate with verification teams to develop testbenches, ensure functional correctness, and debug issues.• Power & Area Optimization: Optimize NoC designs for low-power and area-efficient implementations, working closely with physical design teams.• Integration & Customization: Work on custom NoC configurations, integrating third- party IPs, and tailoring interconnect solutions for specific applications.• Tool & Flow Development: Enhance NoC design methodologies by developing scripts, automation flows, and performance monitoring tools.• Cross-functional Collaboration: Work with chip architects, backend engineers, and software teams to define NoC requirements and optimize for real-world workloads.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementMemory IP Architect / SoC uArchitectID:61252
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan Baru职业类别
Other(IT/Internet/Telecommunications) Engineer, Research & Development(Electrical/Semi-Conductor), Circuit Design(Design/Implementation), Other(Electrical/Semi-Conductor) Engineer
工作内容
We are looking for an experienced Memory IP Architect / uArchitect to lead the architecture and development of next-generation memory solutions for AI, HPC, networking, and custom ASIC applications.This role will drive the definition of memory subsystems, memory controllers, and high-performance SoC memory solutions from concept through silicon.Responsibilities• Define architecture and specifications for Memory IP and SoC subsystems.• Lead memory architecture for DDR5, LPDDR5X/LPDDR6, HBM3E/HBM4, and cache subsystems.• Drive architecture trade-offs across performance, power, area, and cost.• Develop performance models and conduct architecture exploration.• Define memory hierarchy, and system-level optimization strategies.• Collaborate with RTL, DV, DFT, PD, Packaging, Firmware, and Software teams.• Support customer engagements, technical reviews, and roadmap planning.• Guide implementation through silicon bring-up and performance tuning.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementRTL Design Engineer (Junior/Senior)ID:61251
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan Baru职业类别
Other(IT/Internet/Telecommunications) Engineer, Research & Development(Electrical/Semi-Conductor), Circuit Design(Design/Implementation), Other(Electrical/Semi-Conductor) Engineer
工作内容
Position OverviewWe are seeking RTL Design Engineers at Junior/Intermediate and Senior levels to join our Hardware Engineering team, focusing on ASIC and SoC design.The successful candidates will be responsible for RTL development, functional verification, simulation, debugging and design quality throughout the front-end design flow. Depending on experience and seniority, the role will involve implementing well-defined RTL blocks under guidance or independently owning RTL blocks from specification through verification closure and sign-off.Key ResponsibilitiesA. RTL Design & Development- Develop synthesizable RTL using Verilog and/or SystemVerilog in accordance with design specifications and team coding guidelines.- Implement and maintain RTL blocks for ASIC and SoC designs, ensuring functionality, code quality and design efficiency.- Apply synchronous design principles, including clocking, reset strategies, data valid/ready handshaking and clock domain crossing (CDC) techniques.- Design and maintain functional blocks such as finite state machines (FSMs), FIFOs, arbiters, register files, control logic and data paths.- Work with standard bus protocols, including APB and AHB-Lite, with awareness of AXI4.- Consider area, power and performance (PPA) implications when developing and optimizing RTL.- Collaborate with design, verification, physical design (PD), DFT and other cross-functional teams to resolve design issues and improve implementation quality.Junior / Intermediate Level- Implement well-defined RTL blocks based on detailed microarchitecture specifications under the guidance of senior engineers or technical leads.- Develop foundational knowledge of RTL design methodologies, synthesis implications, CDC concepts and low-power design techniques.- Participate in design reviews, identify potential corner cases and proactively raise technical questions or design concerns.- Improve RTL quality and design efficiency based on code review feedback.Senior Level- Independently own RTL blocks from specification review and design implementation through verification closure and sign-off.- Contribute to microarchitecture definition, design specification documentation and technical design reviews.- Optimize RTL for timing closure, area and power through techniques such as pipelining, retiming and appropriate coding strategies.- Implement and evaluate low-power design techniques, including clock gating, isolation cells and retention flops.- Resolve complex RTL design issues and work with physical design teams to address timing and place-and-route feedback.- Provide technical guidance and informal mentoring to junior engineers.B. Functional Verification & Simulation- Develop and execute directed and self-checking SystemVerilog testbenches to verify RTL functionality.- Run simulations, debug functional failures and analyze waveforms using industry-standard tools.- Write SystemVerilog Assertions (SVA) to capture design intent and verify key interface requirements.- Apply functional coverage concepts to assess verification completeness and identify potential coverage gaps.- Collaborate with design verification engineers to investigate issues and ensure design quality.Junior / Intermediate Level- Develop directed testbenches for assigned RTL blocks and execute simulations using tools such as Synopsys VCS, Questa or Icarus Verilog.- Perform waveform debugging using Verdi, DVE or equivalent tools.- Demonstrate basic understanding of UVM concepts, including agents, sequences and scoreboards.- Add basic functional coverage points and develop familiarity with assertions and verification methodologies.Senior Level- Develop and debug more comprehensive testbenches and contribute to UVM agents, sequences and verification environments.- Interpret coverage reports and drive functional coverage closure in collaboration with verification teams.- Apply assertions, assumptions and cover properties, with exposure to formal verification methodologies.- Investigate complex simulation failures and contribute to root-cause analysis across RTL, verification and integration issues.C. Design Quality, Sign-Off & Integration- Ensure RTL designs comply with applicable design specifications, coding standards and quality requirements.- Review simulation results, lint reports and timing information to identify and resolve potential design issues.- Understand the impact of RTL changes on synthesis, timing, integration and downstream implementation.- Collaborate with verification, DFT and physical design teams throughout the design lifecycle.Junior / Intermediate Level- Develop an understanding of static timing analysis (STA), including setup and hold violations.- Resolve common lint warnings and develop familiarity with CDC analysis and synchronizer insertion.- Understand basic DFT concepts, including scan chains and test modes.- Support design reviews and sign-off activities under senior engineer guidance.Senior Level- Interpret STA reports, timing slack and critical paths, and implement RTL changes to address timing issues.- Resolve common CDC and reset domain crossing (RDC) violations and lint issues.- Apply DFT awareness when designing RTL and supporting scan insertion and test mode requirements.- Work closely with physical design teams to resolve implementation-related issues and support design sign-off.- Take ownership of RTL quality and verification closure for assigned blocks.D. Scripting, Automation & Design Tools- Use scripting languages and automation tools to improve design, simulation and debugging efficiency.- Work with existing simulation flows, tool scripts, file lists and build configurations.- Analyze simulation logs and support the maintenance of design and verification workflows.Junior / Intermediate Level- Write basic Python, Tcl or shell scripts to automate repetitive simulation tasks.- Edit existing Makefiles and Tcl run scripts and parse simulation logs.- Demonstrate proficiency in at least one industry-standard simulation tool.Senior Level- Develop and maintain Python, Tcl or shell scripts for simulation automation, regression execution and log analysis.- Manage file lists, hierarchy extraction and simulation flow configurations.- Troubleshoot tool-flow issues and improve automation efficiency where appropriate.- Utilize synthesis and formal verification tools as required by the project.E. Technical Collaboration & Continuous Improvement- Collaborate with cross-functional engineering teams to support successful ASIC/SoC design implementation.- Participate in design reviews, technical discussions and knowledge-sharing activities.- Maintain clear design documentation and communicate technical issues, progress and blockers effectively.- Continuously improve technical knowledge of RTL design, verification methodologies and EDA tools.Junior / Intermediate Level- Work collaboratively within an established design team, seek clarification when requirements are unclear and incorporate feedback from senior engineers.- Provide timely progress updates and proactively communicate design issues or blockers.Senior Level- Drive technical discussions for assigned RTL blocks and document design decisions and implementation considerations.- Coordinate closely with design verification, DFT, physical design and software teams to resolve technical issues.- Mentor junior engineers and contribute to improving team design practices.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementTesting ManagerID:61213
15,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru职业类别
Purchase/Procurement(Admin & Management), Process Engineer(Electrical/Semi-Conductor), Project Engineer(Electrical/Semi-Conductor), Production Management(Mechanical), Production Technology(Electrical/Semi-Conductor), QC/QA(Electrical/Semi-Conductor)
工作内容
• Provide support and enhancements for testing technology in manufacturing plants.• Lead the setup and maintenance of test environments in PCBA manufacturing plants according to test plans.• Lead detailed analysis and accurate identification of issues discovered during testing in PCBA manufacturing plants, discuss defect resolution solutions with developers, and be familiar with analytical tools such as SPC, DOE, and GR&R.• Lead the analysis of functional defects in products during the testing phase and propose improvement measures.• Suggest further improvements for products and evaluate the feasibility of improvement plans.• Manage and maintain testing tools, automation systems, and networked systems in PCBA manufacturing plants.• Any other tasks as assigned by Management.
福利制度
Salary: RM15,000 - RM20,000
AL: Starting from 14 days
MC: 14 / 18 / 22 days
<Other benefits>
• Meal subsidy
• Fixed allowances: Phone, transport
• After confirmation: Medical insurance, health screening, dental/optical (They will share more during interview session)
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