101 Jobs: Job Vacancies for Engineer(Electrical/Semi-Conductor) Positions
Product Development EngineerID:59500
3,500 MYR ~ 5,500 MYRPeraiJob Description
Job SummaryThe Product Development Engineer is responsible for developing new products based on customer requirements, providing technical support, improving manufacturing processes, and ensuring product quality and compliance.The role involves close collaboration with Sales, Production, and customers to ensure successful product development and implementationProduct Development• Develop new products based on customer requirements• Review technical drawings and specifications• Prepare product BOM and technical documents• Conduct feasibility study and risk assessmentTechnical Support• Provide technical support to Sales and Production teams• Assist in customer technical discussions• Handle product-related complaints and root cause analysisProcess & Quality Improvement• Work closely with Production to improve manufacturing processes• Monitor product performance and recommend improvements• Participate in trial runs and sample validation• Support cost reduction initiativesDocumentation & Control• Maintain product specifications and engineering records• Prepare ECN (Engineering Change Notice)• Ensure compliance with quality standards (ISO / IATF if applicable)Coordination & Travel• Coordinate technical matters with overseas suppliers and customers, particularly in China.• Occasional travel to China may be required for technical discussions, supplier visits, or project follow-up.
Benefit
- Annul Leave 10 days onwards
- Medical Leave 14 days onwards
- Hospitalization leave 60 days
- Insurance Coverage
- Panel Clinic
- Performance Bonus
- Yearly Increment【Japanese speaker】Environmental, Health & Safety (EHS) ManagerID:58336
10,000 MYR ~ 13,000 MYRMont KiaraJob Description
This role is to supervise EHS activities at target subsidiaries to build an effective environmental and safety management system in Southeast Asia, supporting the Group's Purpose & Values.- Disseminate the group's EHS policy and management system, aiming to standardize and enhance the quality of EHS management.- Support EHS activities at target subsidiaries to achieve zero accidents, and ensure timely sharing of accident and disaster information within the entire Resonac group.- Strive for zero EHS compliance violations in Southeast Asia by establishing an independent regional EHS audit framework and monitoring management status.- Foster greater communication among target subsidiaries by organizing EHS forums and strengthening EHS initiatives at each subsidiary.- Educate and train local staff to perform EHS duties at the Southeast Asia RHQ, maintaining and enhancing the region's EHS capabilities.- Any other ad-hoc duties as assigned
Benefit
Benefits:
-EPF, Socso, EIS
-Car Park is subsidised by company
-Bonus: 1-2 months, depending on company and individual’s performance.
-Mileage claim RM0.60/km
Employee benefits：
-business trip claimSr Memory Circuit Design EngineerID:59447
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Memory Circuit Design Engineer to design and verify high-performance, low-power SRAM and/or multi-port Register Files (RF) macros for integration into Memory Compiler software. You will own transistor-level design and simulations from specification through silicon correlation.Key Responsibilities• Design SRAM and/or multi-port Register Files (RF) circuits at transistor level (bitcell and periphery). • Define memory architecture/topology to meet power, performance, area, yield and Vmin targets.• Run schematic capture & SPICE simulations across PVT corners & Monte Carlo to close read/write margins.• Analyze & optimize critical paths (decoders, wordline drivers, sense amps, write drivers, IO) for speed & robustness.• Create concise margin/performance reports & track design closure metrics.• Drive post-layout verification with extraction & sign-off simulations; partner with layout for pitch- matched arrays.• Work with Design Automation/Software Team/EDA vendor• To integrate Memory circuits into Memory Compiler system• To automate/generate collateral views & timing/power models (Liberty/LEF/Verilog or equivalent)• Support silicon bring-up, characterization and simulation-to-silicon correlation.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Silicon Validation EngineerID:59446
8,000 MYR ~ 19,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Silicon Validation Engineer to lead silicon bring-up and post-silicon characterization of new Testchips. This hands-on lab role drives test development, automation, data analysis, and cross-team debug closure from power-on to characterization sign-off.Key Responsibilities• Lead Day-0/Day-1 bring-up: safe power-up, clocks/resets, basic access, and smoke tests on first silicon.• Define and execute post-silicon validation/characterization plans with clear milestones and pass/fail criteria. • Develop and deploy silicon tests (bare-metal/low-level software) and maintain repeatable test procedures. • Build automation for test execution, data capture, and regression (Python preferred).• Collect and analyze characterization data (e.g., performance, power, voltage/temperature margins); summarize trends and anomalies.• Triage and debug silicon failures; drive root-cause with design/verification/firmware teams and validate fixes/workarounds.• Improve debug efficiency by proposing/leveraging on-chip observability (registers, counters, logs) and lab measurement methods.• Document lab setup, test methods, results, and silicon errata; create silicon reports; communicate status, risks, and recommendations.• Define specifications for eval/char boards.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Staff IP Logic Design EngineerID:59445
8,000 MYR ~ 15,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
The Senior IP Logic Design Engineer will be responsible for the design and implementation of logic design, microarchitecture definition, RTL coding, IP releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also functional validation through black box and white box validation, FPV validation, functional validation as well as emulations.Key Responsibilities:1. IP Design Responsibility• Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.• Ability to produce testplans to cover design requirement2. IP Quality Responsibility• Ability to execute design validations, FPV, lintra, CDC and etc tools3. IP Releases• Owning the IP Releases for customer release depending on the assignment
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior/Staff/Principal Engineer, Circuit DesignID:59444
6,500 MYR ~ 8,500 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
• Design and implement high speed interfaces and complex mixed-signal circuits using cutting-edge CMOS tech and EDA tools.• Design block IO blocks such as compensation circuit, reference voltage, transmitters and receivers.• Sub blocks include and not confined to , high speed serializers and deserializers, high speed levelshifters , predrivers , drivers , Feed Forward Equalization , DFE , CTLE.• Block to pass rigorous quality and reliability like EM-IR , Aging , Overstress• Run initial SI analysis and IBIS/IBIS-AMI creations.• Timing closure using Prime-Time or equivalent methods.• Work on serial and parallel interfaces.• Work closely with mask designers to deliver the physical design and assist with silicon evaluation.• Perform architecture studies, circuit designs & simulations, floor-planning, instructing mask designers, reliability verifications and silicon bring-up.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSales & Marketing EngineerID:59384
4,000 MYR ~ 6,000 MYRBukit MinyakJob Description
- Drives sales growth through technical consultation, customer engagement, and end-to-end salesmanagement. - Develops new business opportunities, supports client needs, and builds lasting partnerships to achieve company objectives.- Manage full process of sales cycle, from lead generation, cold calling, and consultation to closing order.- Formulate and execute sales strategies to reach company's sales goals and key projects.- Prepare formal reports and presentations to customers.- Assist the S&M Team to do cost estimation, prepare technical submission, proposal, and sales and market potential forecast.- Seek out services and products opportunities that will enhance customer success and generate revenue. - Maintain accurate, complete, up-to-date, and insightful client business profiles to be shared with senior management.- Assist in delivering quality services to clients and to ensure services provided are timely and precise according to clients' business needs, specifications and company's quality standards.- Keep up to date with market trends and new development using information for business development. - Work closely with other departments for development of suitable marketing material to support the distribution of company products and services.
Benefit
- Allowances： Fix monthly allowance of travelling + Phone Allowance RM150 after confirmation
- 1-month contractual bonus
- Performance bonus - based on company performance & top management decision【Japanese Speaker】Service Engineer (PG)ID:59433
4,000 MYR ~ 6,000 MYRBayan LepasJob Description
Responsible for after-sales services, such as maintenance machines, preservation on client site. (Especially electric companies)Product:- Track & Trace, Serialization, Checkweigher, X-ray Inspection Equipment- Tablet/Capsule Visual Inspection System- Capsule Filling MachineCustomer/Area: Manufacturing companiesDetails- Visit clients for the actual installation and troubleshooting issues.- Hear and contact service needs or technical issues from clients on the customer site - Work on customer issues(including technical matters), identify root cause, and suggest a solution- Execution management of service provision
Benefit
- Bonus : (2~3 Months, depending on your performance)
- Salary Increment
- Car Allowance
- Traveling claim available
- Medical fee claimable
- AL: 12 days if employed for less than two 2years
- MC: 14 days if employed for less than two 2years
- Over time allowance
- Traveling Allowance
(RM70 per day in Malaysia, RM150 per day in Asia Country, RM200 per day in Other Area)NoC Senior Design EngineerID:59416
8,000 MYR ~ 15,000 MYRBayan Lepas, Bayan BaruJob Description
Role Overview We are seeking Senior Design Engineer specializing in Network-on-Chip (NoC) to join our cutting-edge semiconductor team. This role involves architecting, designing, and optimizing NoC interconnect solutions for high-performance chips. You will work closely with architects, verification engineers, and software teams to deliver scalable, efficient, and low-latency interconnect designs. Job Description: • NoC Architecture/Micro-architect & Design: Develop and optimize high-performance, scalable, and low-latency NoC solutions for SoCs and multi-core processors. • Performance Analysis: Conduct traffic modeling, simulation, and bottleneck analysis to optimize NoC throughput and latency. • Verification & Validation: Collaborate with verification teams to develop testbenches, ensure functional correctness, and debug issues. • Power & Area Optimization: Optimize NoC designs for low-power and area-efficient implementations, working closely with physical design teams. • Integration & Customization: Work on custom NoC configurations, integrating third-party IPs, and tailoring interconnect solutions for specific applications. • Tool & Flow Development: Enhance NoC design methodologies by developing scripts, automation flows, and performance monitoring tools. • Cross-functional Collaboration: Work with chip architects, backend engineers, and software teams to define NoC requirements and optimize for real-world workloads.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior RTL Design EngineerID:59415
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan BaruJob Description
Role DescriptionThis is a full-time on-site role based in Penang for a Senior RTL Design Engineer specializing in Memory PHY and Controller IP.. The engineer will take ownership of logic sub-blocks within the PHY, contributing to RTL implementation, functional verification, and timing/power constraint definition. The role requires close collaboration with design verification (DV), firmware, and physical design teams to ensure high-quality, high-speed RTL that meets power, performance, and area (PPA) goals.The candidate should have a strong foundation in RTL design, timing analysis, and design methodology best practices, and be capable of driving design closure through disciplined debugging, scripting, and continuous flow improvements.Key Responsibilities1. Block Ownership and RTL Design Implementation• Take ownership of assigned logic sub-blocks within the Memory PHY or Controller IP.• Contribute to RTL design, code review, and integration in collaboration with PHY and full-chip design teams.• Ensure compliance with architecture specifications and coding guidelines.• Understand PHY–Firmware interaction for training, calibration, and initialization sequences.• Develop local testbenches to functionally verify assigned PHY sub-blocks.• Collaborate with DV engineers to debug simulation failures, analyze waveforms, and identify root causes for corner-case issues.2. Behavioral Modeling and Verification Support• Develop and maintain behavioral models for PHY sub-blocks.• Ensure equivalence between behavioral models and schematics through established equivalence-check (LEC/FEV) flows.• Provide model updates to align with design and architectural changes.3. Constraint and Power Intent Definition• Participate in the creation and validation of SDC (timing) and UPF (power intent) files for sub-blocks and/or the top-level PHY.• Validate constraint correctness and ensure smooth handoff to STA and physical design teams.4. Static Verification (Lint / CDC / RDC)• Run Lint, CDC, and RDC checks for sub-blocks and top-level PHY.• Review and debug violations, provide waivers with technical justification.• Support and guide the design team in interpreting and resolving RDC-related issues.5. Code Coverage and Waivers• Support DV team in achieving code coverage closure, reviewing unhit regions, suggesting test scenarios, and writing justified waivers.• Participate in coverage reviews and track closure progress toward sign-off.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
