140 Jobs: Manufacturing(Electronics/Semiconductors)
Senior Electric Engineer ID:55979
9,000 MYR ~ 11,000 MYRPeraiJob Description
- Plan and Organize: Figuring out the best way to make the products. including planning how much of each part is needed and how to assemble everything efficiently.- Fix Problems: If something goes wrong during production, working to fix it quickly so that the factory can keep making products without big delays.- Improve Processes: looking for ways to make production better, faster, and cheaper, but still keep the quality of the products high.- Ensure Safety: Making sure that the workplace is safe for everyone and that the machines are used correctly.(Japan Side handing Design)- Communicate with clients in Netherlands
Benefit
- EPF, SOCSO provided
- AL:10days(first year), after that additional 2days every year(Maximum 20days)
- MC:14days(first year), after that additional 4days every year(Maximum 22days)
-Transportation allowance:(RM100-200/month depends on range)
-Meal Allowance: (RM100/per month)
-Medical Allowance: RM50/per 1time(unlimited)
-Canteen
-Insurance
-Uniform ＆ Shoes
-Long-service awardPhysical Design Lead EngineerID:60207
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Physical Design Lead to own and drive the end-to-end physical implementation of testchips and high-speed interface subsystems such as DDR/LPDDR PHY, HBM PHY, and UCIe from netlist through tape-out-ready GDSII on leading-edge process nodes. This is a technical lead role: candidate is expected to take full ownership of implementation scope, mentor junior PD engineers, define methodology, and drive cross-functional coordination with RTL design, DFT, analog/custom layout, and verification teams. Seniority level to be determined by experience.Key Responsibilities• Own end-to-end physical implementation of assigned testchip or high-speed interface subsystem (DDR/LPDDR, HBM, UCIe, or equivalent): floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and chip finishing through to GDSII stream-out.• Coordinate timing closure across all functional modes and PVT corners with the dedicated full-chip STA owner; provide timing-aware physical implementation decisions, flag routing and placement contributors to timing degradation, and execute physical ECOs as directed.• Lead chip-level or subsystem-level floorplan definition: partition boundaries, I/O ring assembly, hard IP (PHY, memory, custom analog) placement, power domain planning, and bump/pad assignment; balance area, routability, and signal-integrity constraints.• Define and enforce the physical design methodology and flow for the team: synthesis-to-P&R handoff conventions, ECO management, signoff checklists, and documentation standards; develop and maintain flow automation scripts for regression, reporting, and incremental ECO runs.• Drive power integrity sign-off: static and dynamic IR-drop analysis (Redhawk/Voltus or equivalent), EM rule compliance, power strapping strategy, and decap insertion; collaborate with circuit and layout teams to resolve violations.• Coordinate physical verification closure (DRC/LVS/ERC/Antenna) using Calibre or equivalent, including custom analog and mixed-signal IP integration; manage foundry rule deck updates and waiver documentation.• Interface with RTL designers, DFT engineers, and analog/custom layout engineers to align on design constraints, resolve integration issues, and ensure clean handoff at each project milestone; represent physical design in architecture and tapeout readiness reviews.• Mentor and technically guide junior and mid-level physical design engineers; review their floorplans and closure strategies; provide actionable feedback and escalate risks proactively to the program lead.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSales ManagerID:60202
6,000 MYR ~ 10,000 MYRBangi/KajangJob Description
- Be the front line of sales, responsible for acquiring new customers and driving business growth.- Drive new business acquisition, focusing on new customer portfolios and opportunities within group companies.- Act as primary liaison between customers and internal stakeholders, managing day-to-day transactions and long-term relationships.- Analyze sales pipelines, forecasts, and demand trends, proactively identifying risks and growth opportunities.- Lead new project implementation from RFQ through SOP, ensuring alignment with customer requirements, timelines, and quality standards.- Manage end-to-end project execution while coordinating with internal teams and building strong customer relationships.- Prepare and present timely sales and project reports, including performance, status updates, and risk tracking.- For Manager level: develop sales strategies, mentor team members, and oversee strategic negotiations and key customer engagements.
Benefit
- AL: Starting from 14days
- MC: Starting from 14 days
- EPF, SOCSO
- Performance Bonus
- Travel expenses claimable
- Salary IncrementSenior Planning Executive (Contract)ID:60199
5,000 MYR ~ 7,000 MYRBayan LepasJob Description
- Plan, administer and coordinate when receive new orders.- Oversee company vision inclusive of specific Key Performance Indicators (KPI) on quality, production, on time delivery, customers’ satisfaction, continuous improvement and profitability.- Participate in decision making of Master Production Schedule (MPS) loading through proper materials’ sizing.- Analyze, maintain, and execute Materials Requirement Plan (MRP).- Continuously monitor and verify the material pipeline to ensure MRP requirements are met.- Run daily systems reports to determine material shortages that need to be expedited.- Follow-up with appropriate Buyer to ensure materials are available to support Manufacturing use per load plan.- Performs material and capacity analysis in establishing a production schedule for each order, and communicates/resolves related issues.- Analyze potential impact of forecast and production schedule changes on component procurement and production volume.- Ensure materials availability to support production per the MPS through MRP execution, on-time delivery, and coordination of materials movement through receiving to Manufacturing.- Ensure all customers’ Engineering Change Notices (ECN) are implemented in a timely manner.- Monitors material status on upcoming orders and flags and release orders as daily release schedule is defined.- Identify and appropriately address materials supply issues.- Plan and schedule for each Work Order/Job Traveller according to customers’ demand.- Provide Month End Closing Stock to Finance Department.- Work closely with Manufacturing Supervisor and Manufacturing Manager to meet customers’ satisfaction and requirements.- Assist Planning Manager in planning and control production to meet customers’ requirements.
Benefit
- Transport allowance
- Medical Claim
- Optical/ Dental Claim
- Annual Leave – 14 days
- Life insurance and HospitalizationLogic Design Engineer / RTL Design Engineer (Senior/Staff/Principal)ID:60086
8,000 MYR ~ 35,000 MYRBayan Lepas, Bayan BaruJob Description
Job SummaryThe Logic Design Engineer will be responsible for the architecture, design, implementation, and delivery of high-performance digital IPs and subsystems for ASIC/SoC products. The role involves microarchitecture definition, RTL development, functional validation support, timing convergence, and IP release activities while collaborating closely with architecture, verification, physical design, firmware, and system teams to achieve performance, power, area (PPA), and quality targets.The engineer will take ownership of IP or subsystem-level RTL implementation from specification through customer release and contribute to design quality through lint, CDC, formal verification, timing closure, and design reviews.Key Responsibilities1. RTL Design & Microarchitecture• Define and implement block-level or subsystem-level RTL architecture based on product specifications.• Develop high-quality RTL using Verilog/SystemVerilog for ASIC/SoC products.• Participate in microarchitecture definition and document design decisions.• Ensure RTL complies with coding standards, synthesis guidelines, and design methodologies.• Review RTL implementation and participate in peer design reviews.2. Digital IP Development• Own assigned digital IPs or logic blocks from specification through implementation and release.• Design high-speed digital logic capable of achieving timing closure on advanced process nodes.• Collaborate with architects, firmware, and system engineers to ensure correct feature implementation.• Support IP integration into subsystem or SoC environments.3. Design Quality & Verification Support• Produce functional test plans covering design requirements.• Support Design Verification teams in debugging simulation failures and functional issues.• Perform and resolve: Lint, CDC/RDC, Formal Equivalence Verification (FEV), Low Power (UPF/CPF)• Participate in coverage closure and verification reviews.4. Timing & Design Closure• Work closely with Physical Design and STA teams to achieve timing closure.• Support synthesis, timing optimization, clock-domain crossing, and low-power implementation.• Develop and validate timing constraints (SDC) and power intent where applicable.• Resolve setup/hold timing issues and support floorplan optimization.5. IP Release & Documentation• Own IP release deliverables including RTL packages, documentation, and quality sign-off.• Prepare design documentation, architecture specifications, and implementation reports.• Ensure all deliverables meet internal quality standards and customer requirements.6. Cross-functional Collaboration• Work closely with Architecture, DV, Physical Design, Firmware, Validation, and System Engineering teams.• Participate in design reviews, technical discussions, and project planning.• Contribute to continuous improvement of RTL design methodology and automation flows.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementStaff Test Operations EngineerID:60151
7,867 MYR ~ 11,233 MYRKulimJob Description
【Job description】This position is expected to provide Test Operations and Engineering support for products post manufacturing release and deliver operational excellence through cost reductions, OEE, yield and cycle time improvements to achieve our test KPI goals with our Test Manufacturing Sites (Internal and Outsourcing Suppliers) in Malaysia, Thailand, Singapore and across Asia (Taiwan, China, Korea). This position reports into Operations Engineering Department (OED).【Key Responsibilities】- Responsible for Test Operations interface to our company's Product Groups and other functional teams (Supply Chain, Quality, Packaging, Foundry, PMO) across US, Japan, India, Malaysia, and China on all phases of product lifecycle- - Execute daily test operations activities with internal factories and test OSATs to ensure customer delivery fulfillment (i.e. Lot tracking and dispositions, Test Program releases, Hardware Troubleshooting/Repairs, Equipment up-time, Tester Utilization OEE tracking, Continuous Improvement Process, etc)- Coordinate Probe/Final Test transfer from New Product Introduction to High Volume Manufacturing from our company's Product Group groups- Execute new test capacity expansions (tester/ handler/ hardware) to ensure sufficient capacity and meet production demand- Deployment of new tester/handler technology and test solutions to test manufacturing sites from test development- Implement best known practices and process within test manufacturing sites- Drive Gross Margins (OEE, Yield, Retest) improvement initiatives
Benefit
Annual Salary Range :RM94400-RM134800
(Monthly: RM7,867-RM11,233)
*Regarding the employee benefits, please check them directly with the company during your interview.Senior Test Operations Engineer ID:60157
6,417 MYR ~ 9,167 MYRBayan LepasJob Description
【Job description】This position is expected to provide Test Operations and Engineering support for products post manufacturing release and deliver operational excellence through cost reductions, OEE, yield and cycle time improvements to achieve our test KPI goals with our Test Manufacturing Sites (Internal and Outsourcing Suppliers) in Malaysia, Thailand, Singapore and across Asia (Taiwan, China, Korea). This position reports into Operations Engineering Department (OED).【Key Responsibilities】- Responsible for Test Operations interface to Renesas Product Groups and other functional teams (Supply Chain, Quality, Packaging, Foundry, PMO) across US, Japan, India, Malaysia, and China on all phases of product lifecycle- Execute daily test operations activities with internal factories and test OSATs to ensure customer delivery fulfillment (i.e. Lot tracking and dispositions, Test Program releases, Hardware Troubleshooting/Repairs, Equipment up-time, Tester Utilization OEE tracking, Continuous Improvement Process, etc)- Coordinate Probe/Final Test transfer from New Product Introduction to High Volume Manufacturing from Renesas Product Group groups- Execute new test capacity expansions (tester/ handler/ hardware) to ensure sufficient capacity and meet production demand- Deployment of new tester/handler technology and test solutions to test manufacturing sites from test development- Implement best known practices and process within test manufacturing sites- Drive Gross Margins (OEE, Yield, Retest) improvement initiatives
Benefit
Annual Salary Range ::RM77000-RM110000
(Monthly: RM6,417-RM9,167)
*Regarding the employee benefits, please check them directly with the company during your interview.Senior Technical EngineerID:60114
6,000 MYR ~ 7,000 MYRSimpang AmpatJob Description
• Machine assembly, standard part and fabrication part receiving, modifcation, alignment, test run, trouble shooting, installation and customer service as define by department Standard Operating Procedure (SOP), Work Instruction (WI) and Customer Specification. • Perform fine tuning, troubleshooting and analyze machine performance related issues followed by initiating rework or changes required.• Lead, support and coordinate with project team to resolve machine performance issues which is not able to solve by Production team within the allocated deadline/ budget/ quality for each project he is assigned including extra hours as needed. • Feedback and update on time to Production Manager/Mechanical Assembly Manager/Project Manager on project progress and issue encounters as define by Standard Operating Procedure (SOP) and Work Instruction (WI). • Records any information discovered during the fine tuning process that would make the process easier and more efficient; Production Improvement Activity. • Assist Production Manager/Mechanical Assembly Manager on section planning and lead improvement activities. • Develop training program and conduct training for production staffs including subcontractors. • Analyzes assembly blueprint and specification manual (for Build To Print) • Responsible for the use of production facilities and individual tools or equipment as define by Company Tools - Term and Condition. (5%) • Follows safety rules and keeps work area clean and organized as define by 5S Best Practice. • Performs other duties and assignments as instructed by superior from time to time.
Benefit
Salary range: RM6,000 - RM7,000
Fixed allowances:
• Phone allowance
• Petrol allowance
AL: Start with 14 days
SL: 14 / 18 / 22 days
<Other benefits>
• Contractual bonus (pro-rated based on confirmation date)
• Annual bonus (based on individual and company performance)
• Medical insurance
<If OT>
• Daily rate RM16/hour
• Min. 2 hours and above
• Claim on monthly basis
<If travelling>
• Daily allowance (Depending on the country they visit)Memory Layout LeadID:60085
10,000 MYR ~ 12,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Memory Layout Lead to independently execute physical layout design and completion of SRAM and/or Register File (RF) memory macros. You will own full-custom layout from floorplanning through DRC/LVS sign-off, working closely with circuit designers to deliver pitchmatched, tape-out-ready memory blocks. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom physical layout of SRAM and/or multi-port Register File (RF) macros, including bit cell arrays, periphery circuits (decoders, wordline drivers, sense amplifiers, write drivers), and I/O rings, to tape-out quality with limited guidance.• Interpret circuit schematics and layout specifications to implement pitch-matched arrays and hierarchical peripheral blocks, ensuring correct device sizing, poly/diffusion pitches, and metal routing within process constraints.• Drive DRC, LVS, and ERC verification to closure independently; track and resolve violations systematically and maintain sign-off records for assigned memory blocks.• Perform parasitic extraction (PEX) and work directly with circuit designers on post-layout simulation correlation; flag and resolve layout-induced timing or performance degradations.• Implement design-for-manufacturability (DFM) best practices: critical layer fill, dummy device insertion, metal density compliance, and multi-patterning coloring at advanced nodes.• Produce accurate layout deliverables including GDS stream-out, LEF abstracts, and associated documentation; maintain revision history and design review records.• Interface with circuit designers and physical verification engineers to resolve layout-toschematic mismatches and drive end-to-end closure on all assigned memory macros.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementStandard Cells Layout LeadID:60084
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Standard Cells Library Layout Lead to execute the full-custom physical layout of a production-grade standard cell library on leading-edge process nodes. Working from circuit schematics and cell specifications provided by the design team, you will draw, verify, and deliver DRC/LVS-clean cell layouts across combinational, sequential, clock, and physical utility cell types, contributing to a high-quality, tapeout-ready library with minimal day-to-day supervision. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout for a wide range of standard cells: combinational logic, sequential (flip-flops, latches), clock cells, and physical utility cells, across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths, working to cell specifications and floorplans defined by the lead engineer.• Implement FEOL layers (poly, diffusion, fin/nanosheet, contacts, local interconnect) and BEOL routing (M1–M2, vias) in accordance with foundry design rules, ensuring correct device fingering, pin placement, and power rail connections as specified.• Run DRC and LVS verification using Calibre (or equivalent) after each cell completion; independently identify, debug, and resolve violations to achieve a clean sign-off without requiring senior engineer intervention on routine checks.• Ensure correct cell boundary and abutment compliance: maintain CPP-grid alignment, N-well continuity, dummy poly at boundaries, and power rail stitching so that cells abut cleanly in row-based placement without post-assembly DRC failures.• Review layout against parasitic extraction (PEX) results and collaborate with circuit design engineers to address RC-sensitive nodes; make targeted layout adjustments to meet post-extraction simulation targets.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment