21个职位: 招聘信息 机械设计
Senior/Staff Digital Design EngineerID:59719
20,000 MYR ~ 25,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
This role will be responsible for architecting, designing, and verifying complex digital IPs and subsystems for SoCs or ASIC/FPGA-based products. As a senior role, it requires to work closely with system architects, verification, and physical design teams to deliver high-performance, power-efficient, and functionally correct RTL implementations. Overall, the responsibilities cover wider scope encompassing from IP to subsystem level and SOC level global issues.Key ResponsibilitiesArchitect with system engineers to perform:-• Define IP specifications, architecture & test concept.• Specify correct implementation of RTL design and verify digital circuits to deliver high performance, low power, and efficient implementation.• Conduct design reviews and support in documentation.• Support verification engineer to define verification test items.• Support in the roadmap formulation for the sensor IPs.• Support view generation engineers to verify the correctness of the Ips views.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementMechanical Engineer (Business Development and Design Engineer)ID:59645
4,000 MYR ~ 5,000 MYRShah Alam, Other Selangor District工作内容
Mechanical & Structural Design-Perform detailed mechanical and structural design of cranes and material handling systems.Analyze application requirements and translate them into practical and efficient designs.-Execute engineering calculations to ensure structural integrity, performance, and comp liancewith relevant standards.Component Selection-Select appropriate mechanical components based on project requirements.-Ensure all components meet safety, performance, and compliance standards.Design for Manufacturing-Design parts optimized for fabrication, machining, and cost effectiveness.-Collaborate with manufacturing teams to improve production efficiency.-Generate detailed 2D p roduction, 3D models and assembly drawings.Explosion Proof Design-Apply IECEx and ATEX standards in designing equipment for hazardous environments.-Integrate necessary safety feat ures to minimize operational risks.Product Development-Participate in product development activities to ensure the company remains competitive-Established new supplier relationships to broaden supply chain capabilities.Internal Technical Support-Provide technical support to internal departments including oversea subsidiaries.-Prepare technical drawings and documentation for bidding activities-Support development and improvement of factory facilities-Asist in project management tasks-Conduct site technical surveys
福利制度
- Salary: RM4,000 - 5,000
- Work time: Monday to Friday :8.00am to 5.30pm
- Annual increment and bonus (based on performance)
- AL: 14 days
- MC: 14 days
- Accommodation provided (if required)
- Public holidays in accordance with Selangor's official calendar
- EPF / Socso
- Travel allowance: Claim basis
- Medical and miscellaneous claims
- Free parkingMechanical Engineer (Project and Design)ID:59647
4,000 MYR ~ 5,000 MYRShah Alam, Other Selangor District工作内容
Mechanical & Structural Design- Perform detailed mechanical and structural design of cranes and material handling systems.- Analyze application requirements and translate them into practical and efficient designs.- Execute engineering calculations to ensure structural integrity, performance, and comp liance with relevant standards.Component Selection- Select appropriate mechanical compo nents based on project requirements.- Ensure all components meet safety, performance, and compliance standards.Design for Manufacturing- Design parts optimized for fabrication, machining, and cost effectiveness.- Collaborate with manufacturing teams to improve production efficiency.- Generate detailed 2D production, 3D models and assembly drawings.Explosion Proof Design- Apply IECEx and ATEX standards in designing equipment for hazardous environments.- Integrate necessary safety features to minimize operational risks.International Project Management- Coordinate international projects with global EPC clients.- Ensure project progress aligns with schedules and deliverables.Project Documentation- Prepare and manage technical documentation, drawings, certi ficates, and records.- Ensure compliance with client and regulatory documentation requirements.
福利制度
- Salary: RM4,000 - 5,000
- Work time: Monday to Friday :8.00am to 5.30pm
- Annual increment and bonus (based on performance)
- AL: 14 days
- MC: 14 days
- Accommodation provided (if required)
- Public holidays in accordance with Selangor's official calendar
- EPF / Socso
- Travel allowance: Claim basis
- Medical and miscellaneous claims
- Free parkingNoC Senior Design EngineerID:59416
8,000 MYR ~ 15,000 MYRBayan Lepas, Bayan Baru工作内容
Role Overview We are seeking Senior Design Engineer specializing in Network-on-Chip (NoC) to join our cutting-edge semiconductor team. This role involves architecting, designing, and optimizing NoC interconnect solutions for high-performance chips. You will work closely with architects, verification engineers, and software teams to deliver scalable, efficient, and low-latency interconnect designs. Job Description: • NoC Architecture/Micro-architect & Design: Develop and optimize high-performance, scalable, and low-latency NoC solutions for SoCs and multi-core processors. • Performance Analysis: Conduct traffic modeling, simulation, and bottleneck analysis to optimize NoC throughput and latency. • Verification & Validation: Collaborate with verification teams to develop testbenches, ensure functional correctness, and debug issues. • Power & Area Optimization: Optimize NoC designs for low-power and area-efficient implementations, working closely with physical design teams. • Integration & Customization: Work on custom NoC configurations, integrating third-party IPs, and tailoring interconnect solutions for specific applications. • Tool & Flow Development: Enhance NoC design methodologies by developing scripts, automation flows, and performance monitoring tools. • Cross-functional Collaboration: Work with chip architects, backend engineers, and software teams to define NoC requirements and optimize for real-world workloads.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior RTL Design EngineerID:59415
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru工作内容
Role DescriptionThis is a full-time on-site role based in Penang for a Senior RTL Design Engineer specializing in Memory PHY and Controller IP.. The engineer will take ownership of logic sub-blocks within the PHY, contributing to RTL implementation, functional verification, and timing/power constraint definition. The role requires close collaboration with design verification (DV), firmware, and physical design teams to ensure high-quality, high-speed RTL that meets power, performance, and area (PPA) goals.The candidate should have a strong foundation in RTL design, timing analysis, and design methodology best practices, and be capable of driving design closure through disciplined debugging, scripting, and continuous flow improvements.Key Responsibilities1. Block Ownership and RTL Design Implementation• Take ownership of assigned logic sub-blocks within the Memory PHY or Controller IP.• Contribute to RTL design, code review, and integration in collaboration with PHY and full-chip design teams.• Ensure compliance with architecture specifications and coding guidelines.• Understand PHY–Firmware interaction for training, calibration, and initialization sequences.• Develop local testbenches to functionally verify assigned PHY sub-blocks.• Collaborate with DV engineers to debug simulation failures, analyze waveforms, and identify root causes for corner-case issues.2. Behavioral Modeling and Verification Support• Develop and maintain behavioral models for PHY sub-blocks.• Ensure equivalence between behavioral models and schematics through established equivalence-check (LEC/FEV) flows.• Provide model updates to align with design and architectural changes.3. Constraint and Power Intent Definition• Participate in the creation and validation of SDC (timing) and UPF (power intent) files for sub-blocks and/or the top-level PHY.• Validate constraint correctness and ensure smooth handoff to STA and physical design teams.4. Static Verification (Lint / CDC / RDC)• Run Lint, CDC, and RDC checks for sub-blocks and top-level PHY.• Review and debug violations, provide waivers with technical justification.• Support and guide the design team in interpreting and resolving RDC-related issues.5. Code Coverage and Waivers• Support DV team in achieving code coverage closure, reviewing unhit regions, suggesting test scenarios, and writing justified waivers.• Participate in coverage reviews and track closure progress toward sign-off.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementStaff/Senior Staff/Principal Design Verification Engineer (DV)ID:59121
10,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a highly experienced and technically profound Staff Design Verification Engineer to take on a technical leadership role in pre-silicon verification for complex, next-generation Application-Specific Integrated Circuits (ASICs). This role is critical in driving verification excellence, setting technical direction, and mentoring local talent.Key Responsibilities• Verification Strategy & Ownership: Define, implement, and lead the overall verification strategy and test plan development (including functional, coverage, and performance) for complex digital ASIC blocks or full chips, ensuring robust quality before tape-out.• Advanced UVM Testbench: Architect, develop, and maintain advanced, reusable UVM-based verification environments using SystemVerilog to enable constrained-random and coverage-driven verification.• C/C++ Programming: Develop C/C++ test cases, firmware test cases for efficient hardware/software co-verification via DPI-C.• Execution and Triage: Hands-on execution of the verification plan, including test case development, regression management, triage, and expert root-cause analysis of functional bugs in RTL and gate-level simulations.• Coverage and Sign-off: Drive and achieve comprehensive functional and code coverage closure goals, utilizing advanced techniques, writing complex assertions (SVA), and ensuring formal verification compliance.• Technical Mentorship: Act as a subject matter expert and mentor to junior and intermediate verification engineers, fostering best practices in coding, methodology, and debug techniques across the team.• Flow Improvement: Evaluate, select, and develop new verification methodologies, tools, and flows (e.g., formal verification, emulation) to enhance the overall team's productivity and quality.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementPrincipal Engineer/Principal Architect (Design Verification)ID:59120
20,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking an experienced and visionary Principal Engineer/Architect (Design Verification) to lead and drive next-generation design verification strategies, methodologies and execution. The ideal candidate will play a key technical role in shaping DV architecture, methodologies, and execution frameworks to ensure world-class product quality and verification efficiency.Join us if you are a passionate and forward-thinking verification leader who thrives in a fast-paced, innovation-driven semiconductor environment and enjoys mentoring teams, solving complex verification challenges, and influencing design quality and other global engineering teams.Key Responsibilities1. DV Architecture and Methodology Leadership• Define and drive scalable, reusable, and high-efficiency DV architecture and methodology.• Establish verification best practices, including testbench architecture, constrained-random verification, coverage-driven methodologies, and formal verification integration.• Champion automation, regression management, and coverage closure frameworks for continuous efficiency improvement.2. Technical Strategy and Execution• Define verification strategies and verification plans for complex IP design verification (NOC, memory, etc.).• Evaluate and implement state-of-the-art tools, verification techniques, and verification accelerators.• Drive sign-off criteria definition, including functional and code coverage, assertions, and quality metrics.3. Cross-Functional Team Collaboration• Collaborate closely with architecture, design, software teams to ensure robust verification plans and alignment on design intent.• Provide technical guidance to local and global DV teams to standardize and scale best practices.4. Leadership and Mentoring• Mentor and develop technical talent within the DV team, promoting innovation and continuous learning.• Conduct technical reviews, training, and methodology adoption sessions.• Act as a key technical interface with stakeholders and management on DV efficiency and quality metrics.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementCircuit Design Manager / Senior ManagerID:59119
15,000 MYR ~ 35,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
• Lead and manage team that design and implement high speed interfaces and complex mixed-signal circuits using cutting-edge CMOS tech and EDA tools.• Manage deliveries between function groups for example Layout, RTL , DV , Physical Design and SIPI/Package.• Harmonize schedule and end to end delivery• Work closely with business development team to understand future projects and resource needed• First line of clarification and explanation for customer related questions and support• Work with post silicon team for design intent and required validations
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementPrinciple Digital Design Engineer (Logic)ID:59118
20,000 MYR ~ 25,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
This role will be responsible for architecting, designing, and verifying complex digital IPs and subsystems for SoCs or ASIC/FPGA-based products. As a senior role, it requires to work closely with system architects, verification, and physical design teams to deliver high-performance, power-efficient, and functionally correct RTL implementations. Overall, the responsibilities cover wider scope encompassing from IP to subsystem level and SOC level global issues.Key ResponsibilitiesArchitect with system engineers to perform:-• Define IP specifications, architecture & test concept.• Specify correct implementation of RTL design and verify digital circuits to deliver high performance, low power, and efficient implementation.• Conduct design reviews and support in documentation.• Support verification engineer to define verification test items.• Support in the roadmap formulation for the sensor IPs.• Support view generation engineers to verify the correctness of the Ips views.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementIP Logic Design Principle EngineerID:58602
20,000 MYR ~ 35,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
The IP Logic Design Principle Engineer will be responsible for architecting microarchitecture design implementation of an IP, spanning across all IP stack such as application layer, transaction layer, link layer, die to die layer, physical layer. Ability to code verilog / system verilog RTL for complex IP, review RTL coding, orchestra IP development phase for projects from beginning to completion. This includes the ability to technically drive the IP team on Design / Validation in completing technical tasks up to IP releases for customers. Candidate must be also capable of solving high speed timing convergence on various processes and collaborate with cross-functional teams to meet project specifications. The role will drive performance optimization and ensuring design functionality through verification and validation processes.Key Responsibilities:1. IP Microarchitecture Definitions• Define microarchitecture definition across layers and define a clean inter unit partition requirements.• Drive design team to deliver best-in-class IP design that optimizes for area, latency, power and performance.• Ability to distribute and drive the design team to implement high quality design and meeting time to market requirements.2. IP Design Responsibility• Implement very complicated high-speed design which can converge timing convergence at high frequency.• Capable of orchestrating the team on right directions of timing convergence, CDC, lintra and etc. for tools closure.3. IP Quality Responsibility• Review IP design and validation testplan to make sure IP Design is at top notch quality.4. IP Releases• Deep knowledge on Lint and CDC flow and ability to drive the Lint and CDC convergence.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
