175个职位: Manufacturing(Electronics/Semiconductors)

Offset Printing Assistant / LeaderID:59940
3,000 MYR ~ 4,000 MYRPasir Gudang
工作内容
We are looking for a skilled and experienced Printing Assistant Leader to join our growing team. This role is ideal for a hands-on, detail-oriented professional with strong expertise in offset printing and a sharp eye for color accuracy. You will play a key role in supporting production leadership and ensuring high-quality output in a fast-paced manufacturing environment.Key Responsibilities- Operate and manage offset printing machines (Ryobi / RMGT).- Ensure all printed materials meet company quality standards and customer specifications.- Support machine setup, including color matching, registration, and troubleshooting.- Assist in planning and coordinating production schedules to meet deadlines efficiently.- Lead, guide, and train printing operators to maintain high productivity and performance.- Identify and resolve printing defects and machine-related issues promptly.- Ensure compliance with safety regulations and quality control procedures at all times.
福利制度
- Bonus - 2 months (depends on performance)
- AL 8 days
- MC 14 days
- Transportation allowance : Claim Basis
- Free parking
Senior Technical EngineerID:60114
6,000 MYR ~ 7,000 MYRSimpang Ampat
工作内容
• Machine assembly, standard part and fabrication part receiving, modifcation, alignment, test run, trouble shooting, installation and customer service as define by department Standard Operating Procedure (SOP), Work Instruction (WI) and Customer Specification. • Perform fine tuning, troubleshooting and analyze machine performance related issues followed by initiating rework or changes required.• Lead, support and coordinate with project team to resolve machine performance issues which is not able to solve by Production team within the allocated deadline/ budget/ quality for each project he is assigned including extra hours as needed. • Feedback and update on time to Production Manager/Mechanical Assembly Manager/Project Manager on project progress and issue encounters as define by Standard Operating Procedure (SOP) and Work Instruction (WI). • Records any information discovered during the fine tuning process that would make the process easier and more efficient; Production Improvement Activity. • Assist Production Manager/Mechanical Assembly Manager on section planning and lead improvement activities. • Develop training program and conduct training for production staffs including subcontractors. • Analyzes assembly blueprint and specification manual (for Build To Print) • Responsible for the use of production facilities and individual tools or equipment as define by Company Tools - Term and Condition. (5%) • Follows safety rules and keeps work area clean and organized as define by 5S Best Practice. • Performs other duties and assignments as instructed by superior from time to time.
福利制度
Salary range: RM6,000 - RM7,000

Fixed allowances:
• Phone allowance
• Petrol allowance

AL: Start with 14 days
SL: 14 / 18 / 22 days

<Other benefits>
• Contractual bonus (pro-rated based on confirmation date)
• Annual bonus (based on individual and company performance)
• Medical insurance

<If OT>
• Daily rate RM16/hour
• Min. 2 hours and above
• Claim on monthly basis

<If travelling>
• Daily allowance (Depending on the country they visit)
Executive (Material Purchasing)ID:60113
3,400 MYR ~ 4,000 MYRKota Damansara/Petaling Jaya
工作内容
Section MissionPlanning, executing & managing MRO (indirect material purchase) activities and P/L for “CSR assurance”, “Cost rationalization” and “Low cost operation” in collaboration with Panasonic factories, MRO Centers, external business partners and suppliers.Basic FunctionUnderstand corporate policy and factories’ MRO needs, and plan & manage activities to meet factories’ needs in accordance with the policy.Job Responsibilities1. Daily Operations (Online or Offline Purchase Requisition - PR)a) Understand requester requirements and obtain necessary information.b) Conduct sourcing activities, including RFQ / tender processes and arrange site visits when required.c) Ensure fair and equal opportunity for all suppliers and comply with Anti-Bribery & Corruption policies and regulations.d) Follow up on quotations and perform cost comparisons.e) Manage supplier selection and awarding procedures.f) Handle PO management, including delivery follow-up and coordination.2. Support to Operating Units (OU) / Factoriesa) Provide process, operational support, and user training.b) Provide special on-site support to requestors/users when required.3. Master Data Managementa) Manage user / supplier master registration and updates.4. Catalog Managementa) Manage catalog items, including item addition and deletion.b) Manage pricing, including base price, validity period, and periodic price reviews.5. RPA / Automation Supporta) Support RPA/automation to reduce manual errors and speed up processes.
福利制度
- Monthly fixed transport : RM200
- AL 14 days
- ML 14 days
- Medical claims
- Insurance
- Performance bonus
- Yearly increment
Logic Design Verification EngineerID:60088
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru
工作内容
We are seeking to hire Logic Verification Engineer. Familiarity with LPDDR and HBM memory interface IP will be a plus. Seniority level to be determined by experience.Key Responsibilities• Develop and maintain UVM-based verification environments for various IPs, including constrained-random testbenches, protocol-aware monitors, scoreboards, and checkers.• Author detailed verification plans based on specifications, architectural documents, and use-case scenarios; own coverage closure end-to-end.• Drive coverage-driven verification (CDV): functional coverage (covergroups/coverpoints), code coverage (statement, branch, toggle), and SystemVerilog assertions (SVA); identify gaps and close with targeted test scenarios.• Execute gate-level simulations to validate timing, reset sequences, and power-up behavior post-synthesis; apply Formal Property Verification (FPV) to prove critical design properties.• Debug simulation failures in collaboration with RTL designers; document results, coverage metrics, and regression summaries for traceability and sign-off.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
DFT Logic Design EngineerID:60087
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru
工作内容
We are seeking a DFT Logic Design Engineer to implement testability infrastructure across our digital IP portfolio. You will define DFT strategy, integrate scan and BIST structures at the RTL level, and drive fault coverage from early design through silicon bring-up. Seniority level to be determined by experience.Key Responsibilities• Define and own the DFT architecture for digital and mixed-signal blocks: scan insertion strategy, compression ratios, JTAG/IEEE 1149.1 boundary scan, and MBIST/LBIST planning; document and maintain the DFT specification throughout the design cycle.• Develop and integrate DFT RTL (SystemVerilog/Verilog): scan wrappers, BIST controllers, test access ports, and clock/reset control logic; ensure DFT structures are synthesis-clean, timing-closed, and do not degrade functional performance or power.• Run ATPG to generate and validate stuck-at, transition, path-delay, and cell-aware fault pattern sets; achieve and sign off on target fault coverage metrics agreed with the test engineering team.• Collaborate with RTL designers on DFT-aware coding guidelines; perform DFT rule checking, CDC analysis, and Lint to identify and resolve testability violations early in the design cycle before netlist handoff.• Support physical design handoff: provide scan chain ordering recommendations, validate DFT netlist post-layout (LEC, STA), and resolve DFT-related ECOs during timing closure and tapeout.• Support post-silicon validation and ATE bring-up: work with test engineers to load and debug ATPG patterns on ATE platforms, analyze yield data, and triage failing patterns back to root-cause RTL or physical design issues.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Memory Layout Designer/LeadID:60085
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru
工作内容
We are seeking a Memory Layout Designer to independently execute physical layout design and completion of SRAM and/or Register File (RF) memory macros. You will own full-custom layout from floorplanning through DRC/LVS sign-off, working closely with circuit designers to deliver pitchmatched, tape-out-ready memory blocks. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom physical layout of SRAM and/or multi-port Register File (RF) macros, including bit cell arrays, periphery circuits (decoders, wordline drivers, sense amplifiers, write drivers), and I/O rings, to tape-out quality with limited guidance.• Interpret circuit schematics and layout specifications to implement pitch-matched arrays and hierarchical peripheral blocks, ensuring correct device sizing, poly/diffusion pitches, and metal routing within process constraints.• Drive DRC, LVS, and ERC verification to closure independently; track and resolve violations systematically and maintain sign-off records for assigned memory blocks.• Perform parasitic extraction (PEX) and work directly with circuit designers on post-layout simulation correlation; flag and resolve layout-induced timing or performance degradations.• Implement design-for-manufacturability (DFM) best practices: critical layer fill, dummy device insertion, metal density compliance, and multi-patterning coloring at advanced nodes.• Produce accurate layout deliverables including GDS stream-out, LEF abstracts, and associated documentation; maintain revision history and design review records.• Interface with circuit designers and physical verification engineers to resolve layout-toschematic mismatches and drive end-to-end closure on all assigned memory macros.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Standard Cells Library Layout Designer/LeadID:60084
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru
工作内容
We are seeking a Standard Cells Library Layout Designer to execute the full-custom physical layout of a production-grade standard cell library on leading-edge process nodes. Working from circuit schematics and cell specifications provided by the design team, you will draw, verify, and deliver DRC/LVS-clean cell layouts across combinational, sequential, clock, and physical utility cell types, contributing to a high-quality, tapeout-ready library with minimal day-to-day supervision. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout for a wide range of standard cells: combinational logic, sequential (flip-flops, latches), clock cells, and physical utility cells, across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths, working to cell specifications and floorplans defined by the lead engineer.• Implement FEOL layers (poly, diffusion, fin/nanosheet, contacts, local interconnect) and BEOL routing (M1–M2, vias) in accordance with foundry design rules, ensuring correct device fingering, pin placement, and power rail connections as specified.• Run DRC and LVS verification using Calibre (or equivalent) after each cell completion; independently identify, debug, and resolve violations to achieve a clean sign-off without requiring senior engineer intervention on routine checks.• Ensure correct cell boundary and abutment compliance: maintain CPP-grid alignment, N-well continuity, dummy poly at boundaries, and power rail stitching so that cells abut cleanly in row-based placement without post-assembly DRC failures.• Review layout against parasitic extraction (PEX) results and collaborate with circuit design engineers to address RC-sensitive nodes; make targeted layout adjustments to meet post-extraction simulation targets.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Custom Layout Designer/LeadID:60083
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru
工作内容
We are seeking an Custom Layout Designer to execute full-custom physical layout of high-performanceanalog/mixed-signal IPs, working from schematic through to tape-out-ready implementation independently andwith limited guidance. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout of analog/mixed-signal IP blocks (bandgap, LDO, PLL, oscillators, I/O, eFUSE, and other Foundation IP blocks) from schematic to tape-out, independently and with limited guidance.• Perform cell-level and block-level floorplanning: power/ground planning, device placement, and routing channel allocation with awareness of signal integrity and parasitic impact on circuit performance.• Apply custom layout best practices: device matching (common-centroid, interdigitation), shielding, guard rings, well taps, and substrate isolation to meet noise, mismatch, latch-up, and reliability requirements.• Run and resolve DRC, LVS, and ERC sign-off using Calibre or equivalent; ensure clean tape-out verification across all required foundry rule decks.• Support or drive parasitic extraction (Calibre xRC or Quantus QRC) and collaborate with the circuit designer to close performance gaps identified in post-layout simulation.• Participate in layout reviews with circuit designers: interpret schematic annotations, critical net callouts, and back-annotate layout-sensitive constraints (e.g., symmetry requirements, shielding needs, critical parasitics).• Manage layout deliverables for assigned IP blocks: track task progress, provide reliable schedule estimates, and flag risks to the design lead proactively.• Maintain organized GDS/OA databases; adhere to layer naming conventions and ensure version-controlled handoff of layout data aligned with IP library delivery standards.• Collaborate with the physical verification team on foundry rule deck updates and process-node-related DRC changes; support layout porting across technology nodes as required.• Meet EM/IR, electrostatic discharge (ESD), and reliability layout rules; adhere to design methodology guidelines and sign-off checklists established for the IP library.• Support testchip integration: contribute layout views for pad ring assembly, coordinate top-level integration with the responsible designer, and assist in post-silicon debug where layout artifacts are suspected.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Design Automation Engineer (Standard Cells Library)ID:60082
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru
工作内容
We are seeking a Standard Cells Library Design Automation Engineer to develop and maintain the characterization flow that supports our standard cell library design team. Working alongside circuit design and layout engineers, you will automate SPICE-to-Liberty characterization runs across PVT corners, execute library QA regressions, and keep the flow reliable and reproducible through every release cycle. This is a hands-on flow-execution role focused on throughput, repeatability, and data quality.Key Responsibilities• Develop, maintain, and execute the standard cell library characterization flow using industry-standard tools (e.g. Cadence Liberate, Synopsys PrimeLib, or equivalent), producing Liberty models across the required PVT corners and Vt flavors.• Automate job submission, corner sweeping, and result collection on compute clusters; monitor runs, triage failures, and re-run incremental jobs efficiently.• Set up and run characterization testbenches and configuration files from cell netlists, .inst definitions, and SPICE models; support the circuit design team by turning around characterization requests on schedule.• Run library QA regressions (Liberty syntax checks, NLDM/CCS consistency, monotonicity, cross-corner sanity) and flag out-of-spec cells back to the design team with clear diagnostic data.• Package and version characterization outputs (.lib, .db) and maintain the release directory structure so that downstream users receive a clean, reproducible drop each cycle.• Write and maintain Python and Tcl scripts for flow glue, report generation, and regression dashboards; keep the flow documentation current.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
Design Automation Engineer (Analog/Mixed-Signal IP)ID:60081
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru
工作内容
We are seeking a Design Automation (DA) Engineer to develop, deploy, and maintain EDA flows, scripting infrastructure, and methodology tooling that accelerate the full lifecycle of analog/mixed-signal IP — from schematic capture and simulation through physical verification, characterization, and customer delivery. The DA Engineer works as an embedded enablement partner to circuit and layout designers, translating manual, repetitive, and error-prone tasks into robust, scalable automation. Seniority level to be determined by experience.Key Responsibilities• Develop and maintain simulation automation and regression flows using ADE-XL/Assembler, Spectre, and/or HSPICE; implement corner, Monte Carlo, and mismatch batch runs, compare results against specification limits, and report pass/fail status to designers.• Develop SKILL/SKILL++ and Python scripts to automate repetitive layout operations: parameterized cell (PCell) authoring, constraint-driven routing, DRC-clean template generation, and pre-tapeout LVS/DRC batch checking.• Own and maintain the physical verification flow: Calibre DRC/LVS/xRC, Pegasus/PVS, and/or Quantus QRC extraction; automate rule deck updates following foundry process revisions, and maintain a documented automated waiver management system.• Develop and maintain IP characterization flows; automate Liberty (.lib) timing/power view generation, IBIS model extraction, and datasheet/specification reporting pipelines for customer delivery.• Support PDK qualification and updates: validate simulation model files, verify PCell correctness after foundry PDK revisions, and communicate technology node constraints (layout-dependent effects, advanced-node DRC restrictions) to circuit and layout designers.• Serve as the primary DA support contact for circuit and layout designers: diagnose tool issues, resolve flow bottlenecks, provide training on automation scripts and new methodologies, and continuously improve designer experience based on feedback.• Manage EDA tool installation, licensing, compute cluster job submission, and tool vendor engagement for issue escalation, new tool evaluation, and methodology co-development.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment