176个职位: Manager
Legal & Risk ManagerID:59706
12,000 MYR ~ 13,000 MYRKota Damansara/Petaling Jaya工作内容
■ JOB SUMMARYOverseeing the Legal and risk matters for the Group. You will be responsible for rendering support, expertise, and advice on various legal, regulatory, compliance, operational, contractual, and corporate legal matters to ensure the continued success of the company.The incumbent must be able to work independently, effectively, and in a fast-paced environment in line with the development in terms of business directions and objectives of the company.■ JOB RESPONSIBILITES1. Prepare, draft, and conduct a comprehensive review of contracts, agreements, letters, and legal documents arising from day-to-day business and operations, commercial and corporate matters, including corporate exercise, mergers and acquisitions, investments, commercial arrangements, collaborations and/or alliances, customer contracts, vendor/supplier contracts etc.2. Develop strategic approach and lead negotiations with counterparties to achieve the best possible options or positions in contract negotiations for the company.3. Analyze and address legal issues, and provide legal advice, and appropriate solutions.4. Safeguard the company against legal risks and violations.5. Participate and lead internal risk and assessment activities.6. Evaluate company procedures and reports to identify concealed or potential risks.7. Create, review, and enhance the company policies and procedures, ensuring implementation and compliance with the rules and regulations.8. Establish documentation system for the safe custody of legal documents and easy retrieval.9. To ensure effective communications with internal and external stakeholders of the Group of companies.10. To undertake any other tasks and assignments directed at the discretionary of the superior.
福利制度
・Basic Salary = RM 12,000 ~ RM 13,000
・AL = <5Y 14d, >5Y 18d
・MC = <2Y 14d, 2~5Y 18d, >5Y 22d
・Group PA, H&S, Term Life Insurance coverage
・Outpatient Medical – RM700/Year
・Car Park provided
・Bonus based on performance
・Group Annual Dinner (join Penang group)QAQC & Production Management ExecutiveID:59695
6,000 MYR ~ 7,500 MYRKota Damansara/Petaling Jaya工作内容
【Responsibilities】- Perform incoming inspection of raw materials, components, and products in accordance with quality standards and specifications- Conduct product evaluation, testing, and validation to ensure compliance with required performance criteriaIdentify, document, and report non-conforming materials or products- Coordinate with suppliers and internal teams to resolve quality issues and implement corrective actions- Support root cause analysis and contribute to continuous improvement initiatives- Maintain accurate inspection records, reports, and quality documentation- Review technical drawings, specifications, and quality requirements for inspection readiness- Collaborate with procurement, production, and engineering teams to ensure quality alignment- Assist in the development and improvement of inspection procedures and quality standards- Participate in audits and ensure compliance with internal and external quality systems- Monitor supplier quality performance and provide feedback for improvement【Memo】- After joining the company, you will be required to travel to our Singapore production site for approximately one month for training purposes. The duration may be extended depending on progress and business needs. This assignment will also involve supporting the transfer of technical know-how from the Singapore production site to Malaysia.- The location of the production site in Malaysia has not yet been finalized. Areas in or around Kuala Lumpur are currently being considered as potential candidates.- Once the production site location is confirmed, you will be assigned there as your primary workplace and will support the site setup and launch activities. Until then, your base will be the Malaysia Kuala Lumpur office, where you will undergo office-based training and may also travel to affiliated companies for additional training, including the assignment mentioned above. In addition to Singapore, business trips to Japan may also be required.- In cases where subcontracting work is carried out in Malacca, you will be expected to provide on-site support through short-term business trips, including possible day trips.
福利制度
• Performance Bonus (depends on the company performance, twice a year and total 1-2 month as average)
• AL:12 days
• MC:14 days
• Medical & Dental Claim(Maximum RM300 yearly)
• Annual Medical Check-Up(Maximum RM500 yearly)Sales Manager (Johor)ID:59657
10,200 MYR ~ 11,200 MYRJohor Bahru工作内容
We are looking for a dynamic and results-driven Sales Manager to lead and grow our Decorative Project business within Southern region. In this role, you will drive sales performance, expand market share, and lead a high-performing sales team to deliver sustainable growth in line with company objectives.This position will be based in Johor and reporting to Senior Sales Manager, Project.Job description:- Develop and execute sales strategies to achieve targets for revenue, gross margin, DSO, and market share within Southern region.- Conduct comprehensive market mapping to identify growth opportunities, monitor market trends, economic indicators, customer demand, and competitor activity.- Lead, coach, and motivate the sales team to achieve objectives, ensuring alignment with company values and culture.- Monitor daily sales activities, track performance metrics, and provide hands-on guidance to drive results.- Build and maintain strong relationships with customers, dealers, contractors, and consultants through regular site visits and project follow-ups.- Resolve customer concerns, support product application and supply matters, and ensure high levels of customer satisfaction.- Analyze monthly sales and collection reports, identify gaps, and implement corrective actions to improve performance.- Monitor collections and DSO to ensure healthy cash flow and financial discipline.- Conduct regular performance reviews and provide constructive feedback to support employee development.- Collaborate closely with internal stakeholders to ensure seamless workflow and customer-centric solutions.
福利制度
- Transport Allowance
- Mobile Claim
- Petrol Card
- Quarterly Incentive
- Annual Leave 15 days
- Medical Leave 14 days
- Medical Insurance
- Medical claim: RM5000/year for outpatient, RM40K/year for hospitalization
- Performance bonus (February)Sr Library Design EngineerID:59656
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Library Design Engineer to own the end-to-end development of a production-grade standard cell library on leading-edge process nodes. You will drive transistor-level design, multi-Vt cell topology, full characterization, and PPA validation delivering robust, sign-off-ready library views to downstream implementation flows. Seniority level to be determined by experience.Key Responsibilities• Design, simulate, and analyze standard cell circuits at transistor level, including combinational, sequential, clock, and physical utility cells across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths.• Perform layout process-node-shift; guide layout clean-up effort and review for DRC/LVS compliance, EM/IR rules, and parasitic awareness at the cell level.• Define & execute characterization flow to generate complete library views & models, covering timing (NLDM/CCS/ECSM), power (dynamic, leakage, internal), noise, and variation-aware models (LVF/SOCV/POCV); ensure Liberty, LEF, and GDS consistency.• Define & execute QA regression to check library quality; validate cell robustness including noise margin, drive strength, X-propagation, and scan/DFT cell correctness; drive STA correlation using PrimeTime or Tempus to confirm model accuracy in real PD flows.• Lead standard cell library IP integration into Testchip, including Testchip circuit and test plan development; support hardware bring-up and debug.• Perform pre/post-silicon correlation & model/design optimization; drive root-cause analysis for first-silicon issues and implement yield/robustness improvements.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr eFUSE Design EngineerID:59655
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking an eFUSE Design Engineer to own the end-to-end development of production-grade eFUSE IP on leading-edge process nodes. You will drive eFUSE array architecture, circuit design, full simulation-based verification, collateral and view generation, and quality checks — delivering robust, sign-off-ready eFUSE IP to downstream SoC integration flows. Bitcell-level design knowledge is valued; direct bitcell design experience is a plus but not required. Seniority level to be determined by experience.Key Responsibilities• Design and architect the eFUSE array circuit, including sense amplifier, reference bias, programming current control, address decoder, column multiplexer, and repair logic; ensure correct functional operation across all PVT corners.• Develop and execute comprehensive simulation plans for the eFUSE macro, covering DC/AC characterization, programming/read margin analysis, retention, endurance, and reliability corner simulations (MC, Mismatch, Aging); validate against product specifications and foundry bitcell models.• Generate and validate all required IP deliverable views and collateral: timing models (Liberty .lib), physical abstracts (LEF/GDS), behavioral models (Verilog), datasheets, and application notes; ensure consistency across all views and compliance with delivery checklist.• Define and execute IP quality checks (QC) and quality assurance (QA) regression suites; run DRC/LVS/ERC/PEX sign-off on the eFUSE macro layout; conduct formal and simulation-based functional verification; ensure all sign-off criteria are met prior to IP release.• Collaborate with the foundry and PDK team on eFUSE bitcell characterization data, SPICE models, and process design rules; translate foundry bitcell specifications and reliability requirements into array-level design constraints.• Support Testchip integration of the eFUSE macro, including test circuit design, programming and read test plan development; assist in hardware bring-up, failure analysis, and silicon–to–simulation correlation.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Analog Circuit Design Engineer (General Purpose I/O) (GPIO)ID:59654
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in GPIO (General Purpose I/O) design as described below. Seniority level to be determined by experience.Key Responsibilities• Own GPIO IP architecture/specs: bidirectional I/O, mixed-voltage/failsafe tolerance, programmable drive strength & slew-rate control, Schmitt-trigger inputs, pull-up/pull-down, bus-keeper/retention, and pad-ring support cells (supply, corner, filler, terminator/diode-breaker, cut cells).• Design and implement transistor-level GPIO circuits: input receiver, output driver, level shifters, predrivers, reference/compensation sub-blocks, analog test hooks.• Ensure robust reliability and quality signoff for I/O cells and rings (ESD, latch-up, EM/IR, aging, overstress, noise immunity and ground-bounce/SSN considerations).• Run comprehensive simulations and verification (PVT corners/Monte Carlo, pre- and post-layout, worst-case timing and functional modes) and drive design reviews with clear documentation.• Develop and release collateral for IP enablement: datasheets, integration guidelines, characterization reports, and models (SPICE/Verilog-A, and IBIS where applicable).• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.• Perform SI/PI and I/O behavior checks at the package/board interface level; support IBIS-based signoff and customer debug as needed.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Analog Circuit Design Engineer (Clocking)ID:59653
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in Clocking as described below. Seniority level to be determined by experience.Key Responsibilities• Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted).• Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting.• Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques.• DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Analog Circuit Design Engineer (High-Speed I/O)ID:59652
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in High-Speed I/O as described below. Seniority level to be determined by experience.Key Responsibilities• Design TX/RX, analog front-end, serializers/deserializers, high-speed level shifters, predrivers/drivers, and termination/impedance calibration blocks.• Equalization: Feed-Forward Equalization (FFE), DFE, CTLE and related adaptation/control loops.• Clocking support for links (e.g., CDR interactions, low-jitter clock generation/distribution as needed by PHY).• SI analysis and creation/validation of IBIS/IBIS-AMI models; channel characterization (insertion loss, return loss, crosstalk) and eye diagram margin assessment.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Support interface integration and sign-off: PPA optimization, reliability checks (e.g., EM/IR, aging/overstress), and timing closure collaboration.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Analog Circuit Design Engineer (Pure Analog)ID:59651
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. Seniority level to be determined by experience.Key Responsibilities• Reference generation: bandgap, bias circuits, reference voltages/currents; high-accuracy, low-noise design techniques.• Low offset / low-noise voltage regulators (LDO) and stability/compensation networks; PSRR and transient response optimization.• Voltage and power monitoring circuits: droop detection, voltage detectors, PowerGood and POR generation, analog sensing, and housekeeping blocks.• Power-management components, linear and/or switching-adjacent blocks, charge pumps, as applicable to the SoC/PHY environment.• Design/support ADC/DAC blocks and associated analog support circuits (sampling, references, amplifiers/comparators, clocking).• Voltage and temperature sensor design and characterization. Bandgap and PTAT-based temperature sensing; process corner detection circuits. Sensor readout, digitization, and calibration techniques.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment【Penang】 Senior Sales ExecutiveID:59632
4,600 MYR ~ 6,000 MYRGelugur, Jelutong工作内容
【Job Responsibilities】• Product handle is Electronic component product• To handle and serve Global Distributors business for E&E (Global Distributors : Avnet, TTI, Future, Arrow ) • Manage and grow existing key accounts through strong relationships and continuous engagement.• Work closely with technical teams to deliver product demonstrations, troubleshooting, and technical presentations.• Collaborate with supply chain and operations teams to manage lead times, product availability, and customer delivery schedules.• Prepare sales forecasts, pipeline updates, and monthly business reports.• Provide timely solutions to customer requirements and coordinate after sales support.
福利制度
Salary range: ~RM4.6K - RM6K
- Annual Leave
- Medical Leave
- Transport Allowance
- Transport to Client Visit (Claimable)
- Company Parking
- Bonus (Depends company performance - avg 2 months)
- Other benefits will be disclose during interview session.
- No sales commission
