425 Jobs: 5-10 years
Standard Cells Layout LeadID:60084
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Standard Cells Library Layout Lead to execute the full-custom physical layout of a production-grade standard cell library on leading-edge process nodes. Working from circuit schematics and cell specifications provided by the design team, you will draw, verify, and deliver DRC/LVS-clean cell layouts across combinational, sequential, clock, and physical utility cell types, contributing to a high-quality, tapeout-ready library with minimal day-to-day supervision. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout for a wide range of standard cells: combinational logic, sequential (flip-flops, latches), clock cells, and physical utility cells, across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths, working to cell specifications and floorplans defined by the lead engineer.• Implement FEOL layers (poly, diffusion, fin/nanosheet, contacts, local interconnect) and BEOL routing (M1–M2, vias) in accordance with foundry design rules, ensuring correct device fingering, pin placement, and power rail connections as specified.• Run DRC and LVS verification using Calibre (or equivalent) after each cell completion; independently identify, debug, and resolve violations to achieve a clean sign-off without requiring senior engineer intervention on routine checks.• Ensure correct cell boundary and abutment compliance: maintain CPP-grid alignment, N-well continuity, dummy poly at boundaries, and power rail stitching so that cells abut cleanly in row-based placement without post-assembly DRC failures.• Review layout against parasitic extraction (PEX) results and collaborate with circuit design engineers to address RC-sensitive nodes; make targeted layout adjustments to meet post-extraction simulation targets.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementCustom (Analog) Layout LeadID:60083
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking an Custom Layout Lead to execute full-custom physical layout of high-performanceanalog/mixed-signal IPs, working from schematic through to tape-out-ready implementation independently andwith limited guidance. Seniority level to be determined by experience.Key Responsibilities• Execute full-custom transistor-level layout of analog/mixed-signal IP blocks (bandgap, LDO, PLL, oscillators, I/O, eFUSE, and other Foundation IP blocks) from schematic to tape-out, independently and with limited guidance.• Perform cell-level and block-level floorplanning: power/ground planning, device placement, and routing channel allocation with awareness of signal integrity and parasitic impact on circuit performance.• Apply custom layout best practices: device matching (common-centroid, interdigitation), shielding, guard rings, well taps, and substrate isolation to meet noise, mismatch, latch-up, and reliability requirements.• Run and resolve DRC, LVS, and ERC sign-off using Calibre or equivalent; ensure clean tape-out verification across all required foundry rule decks.• Support or drive parasitic extraction (Calibre xRC or Quantus QRC) and collaborate with the circuit designer to close performance gaps identified in post-layout simulation.• Participate in layout reviews with circuit designers: interpret schematic annotations, critical net callouts, and back-annotate layout-sensitive constraints (e.g., symmetry requirements, shielding needs, critical parasitics).• Manage layout deliverables for assigned IP blocks: track task progress, provide reliable schedule estimates, and flag risks to the design lead proactively.• Maintain organized GDS/OA databases; adhere to layer naming conventions and ensure version-controlled handoff of layout data aligned with IP library delivery standards.• Collaborate with the physical verification team on foundry rule deck updates and process-node-related DRC changes; support layout porting across technology nodes as required.• Meet EM/IR, electrostatic discharge (ESD), and reliability layout rules; adhere to design methodology guidelines and sign-off checklists established for the IP library.• Support testchip integration: contribute layout views for pad ring assembly, coordinate top-level integration with the responsible designer, and assist in post-silicon debug where layout artifacts are suspected.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Design Automation Engineer (Standard Cells Library)ID:60082
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Standard Cells Library Design Automation Engineer to develop and maintain the characterization flow that supports our standard cell library design team. Working alongside circuit design and layout engineers, you will automate SPICE-to-Liberty characterization runs across PVT corners, execute library QA regressions, and keep the flow reliable and reproducible through every release cycle. This is a hands-on flow-execution role focused on throughput, repeatability, and data quality.Key Responsibilities• Develop, maintain, and execute the standard cell library characterization flow using industry-standard tools (e.g. Cadence Liberate, Synopsys PrimeLib, or equivalent), producing Liberty models across the required PVT corners and Vt flavors.• Automate job submission, corner sweeping, and result collection on compute clusters; monitor runs, triage failures, and re-run incremental jobs efficiently.• Set up and run characterization testbenches and configuration files from cell netlists, .inst definitions, and SPICE models; support the circuit design team by turning around characterization requests on schedule.• Run library QA regressions (Liberty syntax checks, NLDM/CCS consistency, monotonicity, cross-corner sanity) and flag out-of-spec cells back to the design team with clear diagnostic data.• Package and version characterization outputs (.lib, .db) and maintain the release directory structure so that downstream users receive a clean, reproducible drop each cycle.• Write and maintain Python and Tcl scripts for flow glue, report generation, and regression dashboards; keep the flow documentation current.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Design Automation Engineer (Analog Mixed-Signal Design)ID:60081
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan BaruJob Description
We are seeking a Design Automation (DA) Engineer to develop, deploy, and maintain EDA flows, scripting infrastructure, and methodology tooling that accelerate the full lifecycle of analog/mixed-signal IP — from schematic capture and simulation through physical verification, characterization, and customer delivery. The DA Engineer works as an embedded enablement partner to circuit and layout designers, translating manual, repetitive, and error-prone tasks into robust, scalable automation. Seniority level to be determined by experience.Key Responsibilities• Develop and maintain simulation automation and regression flows using ADE-XL/Assembler, Spectre, and/or HSPICE; implement corner, Monte Carlo, and mismatch batch runs, compare results against specification limits, and report pass/fail status to designers.• Develop SKILL/SKILL++ and Python scripts to automate repetitive layout operations: parameterized cell (PCell) authoring, constraint-driven routing, DRC-clean template generation, and pre-tapeout LVS/DRC batch checking.• Own and maintain the physical verification flow: Calibre DRC/LVS/xRC, Pegasus/PVS, and/or Quantus QRC extraction; automate rule deck updates following foundry process revisions, and maintain a documented automated waiver management system.• Develop and maintain IP characterization flows; automate Liberty (.lib) timing/power view generation, IBIS model extraction, and datasheet/specification reporting pipelines for customer delivery.• Support PDK qualification and updates: validate simulation model files, verify PCell correctness after foundry PDK revisions, and communicate technology node constraints (layout-dependent effects, advanced-node DRC restrictions) to circuit and layout designers.• Serve as the primary DA support contact for circuit and layout designers: diagnose tool issues, resolve flow bottlenecks, provide training on automation scripts and new methodologies, and continuously improve designer experience based on feedback.• Manage EDA tool installation, licensing, compute cluster job submission, and tool vendor engagement for issue escalation, new tool evaluation, and methodology co-development.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Analog Circuit Design Engineer (Highspeed IO Buffer LPDDR6)ID:60080
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking an experienced Analog / Mixed-Signal Circuit Design Engineer to develop high-performance High-Speed I/O analog buffer circuits for LPDDR6 memory interfaces, from architecture definition through tapeout and silicon bring-up. The candidate should have strong hands-on expertise in high-speed analog I/O design, with proven ownership of silicon-proven blocks. Seniority level will be determined based on experience.Key Responsibilities• Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits.• Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements.• Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications.• Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off.• Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics.• Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects.• Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control.• Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging).• Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed.• Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Sales ManagerID:60034
4,000 MYR ~ 6,000 MYRBangi/KajangJob Description
- New Customer Development: Proactively identify, prospect, and acquire newcorporate accounts to expand the company’s client base.- Sales Strategy Execution: Develop and implement effective sales strategies toreinforce the company’s logistics sales performance and market share.- Targeting & Lead Generation: Conduct market research to identify potential localand international customers, tailoring logistics solutions to meet their specificneeds.- Relationship Management: Build and maintain strong, long-term relationshipswith key decision-makers at target organizations.- Solution Proposals: Prepare and present comprehensive logistics proposals,including freight forwarding, warehousing, and supply chain managementservices.- Performance Reporting: Monitor sales KPIs and provide regular reports onbusiness development activities and pipeline status.
Benefit
- EPF, SOCSO, EIS provided
- Bonus(Depends on the Performance)
- AL：14days
- MC：14 days
- Transportation Allowance(RM800 Fixed)Food Merchandiser ID:60027
6,000 MYR ~ 7,500 MYRBukit Bintang/KLCCJob Description
1. Product Selection & Assortment Planning2. Buying & Supplier Management3. Sales & Profit Management4. Inventory & Stock Control5. Merchandising & Display6. Promotion & Event Planning7. Customer & Market Insight8. Cross-functional Coordination9. Compliance & Quality Control
Benefit
- Salary: RM6,000 - 7,500
- transportation allowance: claimable (For car 0.6 cent/km)
- fixed phone allowance: Yes, but only Manager position
<Benefits>
EPF/SOCSO
MC:14 days
AL:12 day
Bonus : Once a year, subject to the company performance
Medical claim【Japanese Speakers】QA Enginner/ManagerID:60025
6,000 MYR ~ 7,000 MYRSeri KembanganJob Description
**Job Title:**Japanese Quality Assurance Engineer – Automotive & Electronics Die Casting Products**Company Overview:**Our company is one of the largest Japanese manufacturers in Malaysia, with over 700 employees. Specializing in aluminum die-casting components for the automotive and electronics industries, we are now seeking a Japanese Quality Assurance Engineer to support our continued business expansion. Our operations are stable and resilient to economic fluctuations, thanks to our broad customer base across Malaysia and international markets.We supply high-precision aluminum die-cast components not only for conventional automobiles but also for eco and electric vehicles—sectors poised for further growth.**Products:*** Automotive and motorcycle parts* Computer components* Hydraulic equipment parts* General industrial machinery components(*Note: Aluminum die casting is a technique in which molten metal is injected into a mold to produce precise components.*)**Key Responsibilities:***Internal Quality Assurance:** Manage and monitor quality across all production stages* Implement and lead quality improvement initiatives* Establish and maintain internal quality standards* Conduct on-site inspections and recommend manufacturing improvements when needed*Client-Facing Activities:** Respond to customer inquiries and requests regarding product quality* Investigate issues, coordinate with internal teams, and formulate appropriate countermeasures* Draft related documentation such as manuals when necessary* Participate in discussions on quality standards and specifications with clients**Work Environment:*** Office-based work with regular access to adjacent production facilities* Uniform required during working hours* In-house cafeteria available (meals at lower-than-city prices)**Location:**3377, Taman Industri Selesa Jaya, Balakong, Taman Industri Selesa Jaya, 43300 Seri Kembangan, Selangor, Malaysia**Career Opportunity:**The company employs approximately 20 Japanese professionals, providing strong potential for advancement within the organization.**Business Travel:**Required (based on project needs)
Benefit
**Leave**
* Paid Annual Leave: Yes (increases with years of service)
* Sick Leave: 14 days per year
**Health & Insurance**
* Health/Medical Insurance: Coverage up to RM300 per year (with specific terms and conditions)
* No company-provided health checkups
* Workers’ compensation insurance is provided
**Additional Information**
* Calendar follows Malaysian public holidays
* Company mobile phone provided
* On-site cafeteria available for lunch
* Housing options: Company dormitory available / Housing allowance provided. For details, please refer to the “in-house sharing” section
* Company car available after 3 months of employment, with fuel card provided
* Overtime: Subject to workloadSenior Software Engineer (PLC) ID:60017
6,000 MYR ~ 8,500 MYRBayan BaruJob Description
• Design, development, and implementation of PLC and/or PC based software solutions• Perform system integration, testing and commissioning of advanced control systems for equipment automation system.• Participate in control system requirement analysis.• Involved in drafting of functional specifications and detailed design specification.• Provide technical onsite support to external and internal customers.• Interpret client requirements, identify design parameters, and ensure solutions are implemented accurately and within budget to meet project requirements and schedules• Ensure software issues are resolved in a timely manner
Benefit
Salary package: ~RM5,000 - RM7,000
AL: Starting from 12 days
SL: 14 / 18 / 22 days
<Others>
• Mobile phone reimbursements/transport allowances
• Medical insurance
• Medical claim
*The rest of the benefits, they will be able to share during interview sessionSenior Mechanical Design EngineerID:60011
5,000 MYR ~ 8,000 MYRBayan BaruJob Description
• Conduct equipment design & development work according to customers and internal specifications.• Act as project lead to plan, organize and co-ordinate their respective project’s meetings to review design and ensure projectsare kept to schedule.• Maintain and control relevant documents related to R & D activities per requirements.• Maintain, keep track, and ensure Billed Materials is updated.• Generate detailed 2D/3D drawings• Raise ECN for update of changes to design and drawings and follow up on approval and ECN flow.• Provide technical support to process & production, supply chain & QA for review and troubleshooting of design and drawings
Benefit
Salary package: ~RM5,000 - RM7,000
AL: Starting from 12 days
SL: 14 / 18 / 22 days
<Others>
• Mobile phone reimbursements/transport allowances
• Medical insurance
• Medical claim
*The rest of the benefits, they will be able to share during interview session