53个职位: 招聘信息 其他(半导体)工程师
Sr Memory Circuit Design EngineerID:59447
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Memory Circuit Design Engineer to design and verify high-performance, low-power SRAM and/or multi-port Register Files (RF) macros for integration into Memory Compiler software. You will own transistor-level design and simulations from specification through silicon correlation.Key Responsibilities• Design SRAM and/or multi-port Register Files (RF) circuits at transistor level (bitcell and periphery). • Define memory architecture/topology to meet power, performance, area, yield and Vmin targets.• Run schematic capture & SPICE simulations across PVT corners & Monte Carlo to close read/write margins.• Analyze & optimize critical paths (decoders, wordline drivers, sense amps, write drivers, IO) for speed & robustness.• Create concise margin/performance reports & track design closure metrics.• Drive post-layout verification with extraction & sign-off simulations; partner with layout for pitch- matched arrays.• Work with Design Automation/Software Team/EDA vendor• To integrate Memory circuits into Memory Compiler system• To automate/generate collateral views & timing/power models (Liberty/LEF/Verilog or equivalent)• Support silicon bring-up, characterization and simulation-to-silicon correlation.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Silicon Validation EngineerID:59446
8,000 MYR ~ 19,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Silicon Validation Engineer to lead silicon bring-up and post-silicon characterization of new Testchips. This hands-on lab role drives test development, automation, data analysis, and cross-team debug closure from power-on to characterization sign-off.Key Responsibilities• Lead Day-0/Day-1 bring-up: safe power-up, clocks/resets, basic access, and smoke tests on first silicon.• Define and execute post-silicon validation/characterization plans with clear milestones and pass/fail criteria. • Develop and deploy silicon tests (bare-metal/low-level software) and maintain repeatable test procedures. • Build automation for test execution, data capture, and regression (Python preferred).• Collect and analyze characterization data (e.g., performance, power, voltage/temperature margins); summarize trends and anomalies.• Triage and debug silicon failures; drive root-cause with design/verification/firmware teams and validate fixes/workarounds.• Improve debug efficiency by proposing/leveraging on-chip observability (registers, counters, logs) and lab measurement methods.• Document lab setup, test methods, results, and silicon errata; create silicon reports; communicate status, risks, and recommendations.• Define specifications for eval/char boards.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Staff IP Logic Design EngineerID:59445
8,000 MYR ~ 15,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
The Senior IP Logic Design Engineer will be responsible for the design and implementation of logic design, microarchitecture definition, RTL coding, IP releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also functional validation through black box and white box validation, FPV validation, functional validation as well as emulations.Key Responsibilities:1. IP Design Responsibility• Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.• Ability to produce testplans to cover design requirement2. IP Quality Responsibility• Ability to execute design validations, FPV, lintra, CDC and etc tools3. IP Releases• Owning the IP Releases for customer release depending on the assignment
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior/Staff/Principal Engineer, Circuit DesignID:59444
6,500 MYR ~ 8,500 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
• Design and implement high speed interfaces and complex mixed-signal circuits using cutting-edge CMOS tech and EDA tools.• Design block IO blocks such as compensation circuit, reference voltage, transmitters and receivers.• Sub blocks include and not confined to , high speed serializers and deserializers, high speed levelshifters , predrivers , drivers , Feed Forward Equalization , DFE , CTLE.• Block to pass rigorous quality and reliability like EM-IR , Aging , Overstress• Run initial SI analysis and IBIS/IBIS-AMI creations.• Timing closure using Prime-Time or equivalent methods.• Work on serial and parallel interfaces.• Work closely with mask designers to deliver the physical design and assist with silicon evaluation.• Perform architecture studies, circuit designs & simulations, floor-planning, instructing mask designers, reliability verifications and silicon bring-up.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementField Application Engineer (FPGA)ID:59412
5,100 MYR ~ 6,100 MYRGeorgetown工作内容
• Drive design in and product promotional activities in Vietnam• Spearhead the development of new demand creation customers• Align and coordinate with suppliers for all technical promotion activities• Excellent troubleshooting skills to provide in-depth technical support to customers• Conduct seminars and training to customers
福利制度
- 12 days AL
- Medical Claim RM 50 per visit, RM 500 max per year
- Dental RM 200 per year
- Annual Health Screening
- Bonus pay-out twice a year
- Kick-off meeting tripNoC Senior Design EngineerID:59416
8,000 MYR ~ 15,000 MYRBayan Lepas, Bayan Baru工作内容
Role Overview We are seeking Senior Design Engineer specializing in Network-on-Chip (NoC) to join our cutting-edge semiconductor team. This role involves architecting, designing, and optimizing NoC interconnect solutions for high-performance chips. You will work closely with architects, verification engineers, and software teams to deliver scalable, efficient, and low-latency interconnect designs. Job Description: • NoC Architecture/Micro-architect & Design: Develop and optimize high-performance, scalable, and low-latency NoC solutions for SoCs and multi-core processors. • Performance Analysis: Conduct traffic modeling, simulation, and bottleneck analysis to optimize NoC throughput and latency. • Verification & Validation: Collaborate with verification teams to develop testbenches, ensure functional correctness, and debug issues. • Power & Area Optimization: Optimize NoC designs for low-power and area-efficient implementations, working closely with physical design teams. • Integration & Customization: Work on custom NoC configurations, integrating third-party IPs, and tailoring interconnect solutions for specific applications. • Tool & Flow Development: Enhance NoC design methodologies by developing scripts, automation flows, and performance monitoring tools. • Cross-functional Collaboration: Work with chip architects, backend engineers, and software teams to define NoC requirements and optimize for real-world workloads.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior RTL Design EngineerID:59415
10,000 MYR ~ 20,000 MYRBayan Lepas, Bayan Baru工作内容
Role DescriptionThis is a full-time on-site role based in Penang for a Senior RTL Design Engineer specializing in Memory PHY and Controller IP.. The engineer will take ownership of logic sub-blocks within the PHY, contributing to RTL implementation, functional verification, and timing/power constraint definition. The role requires close collaboration with design verification (DV), firmware, and physical design teams to ensure high-quality, high-speed RTL that meets power, performance, and area (PPA) goals.The candidate should have a strong foundation in RTL design, timing analysis, and design methodology best practices, and be capable of driving design closure through disciplined debugging, scripting, and continuous flow improvements.Key Responsibilities1. Block Ownership and RTL Design Implementation• Take ownership of assigned logic sub-blocks within the Memory PHY or Controller IP.• Contribute to RTL design, code review, and integration in collaboration with PHY and full-chip design teams.• Ensure compliance with architecture specifications and coding guidelines.• Understand PHY–Firmware interaction for training, calibration, and initialization sequences.• Develop local testbenches to functionally verify assigned PHY sub-blocks.• Collaborate with DV engineers to debug simulation failures, analyze waveforms, and identify root causes for corner-case issues.2. Behavioral Modeling and Verification Support• Develop and maintain behavioral models for PHY sub-blocks.• Ensure equivalence between behavioral models and schematics through established equivalence-check (LEC/FEV) flows.• Provide model updates to align with design and architectural changes.3. Constraint and Power Intent Definition• Participate in the creation and validation of SDC (timing) and UPF (power intent) files for sub-blocks and/or the top-level PHY.• Validate constraint correctness and ensure smooth handoff to STA and physical design teams.4. Static Verification (Lint / CDC / RDC)• Run Lint, CDC, and RDC checks for sub-blocks and top-level PHY.• Review and debug violations, provide waivers with technical justification.• Support and guide the design team in interpreting and resolving RDC-related issues.5. Code Coverage and Waivers• Support DV team in achieving code coverage closure, reviewing unhit regions, suggesting test scenarios, and writing justified waivers.• Participate in coverage reviews and track closure progress toward sign-off.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementElectrical Engineer (Bentong)ID:59399
7,000 MYR ~ 12,000 MYRPahang工作内容
We are seeking a highly skilled and proactive Electrical Engineer to join our technical team in Bentong. You will be responsible for ensuring the reliability, safety, and efficiency of the electrical power distribution systems and specialized manufacturing equipment at our rubber thread production facility. The ideal candidate will have hands-on experience with high-voltage systems and the technical grit to manage the unique electrical demands of a continuous latex processing plant.Key Responsibilities- Power System Management: Oversee the operation, maintenance, and troubleshooting of the 11kV Generator, as well as all High Voltage (HV) and Low Voltage (LV) distribution boards and transformers.- Production Support: Maintain and optimize electrical components specific to rubber thread manufacturing, including precision heating elements, high-speed winding motors, and centrifugal systems.- Instrumentation & Control: Calibrate and repair instruments related to temperature control, flow meters, and pressure sensors essential for stable latex processing.- Preventive Maintenance: Design and execute scheduled maintenance programs to minimize downtime in a 24/7 manufacturing environment.- Safety & Compliance: Ensure all electrical installations and practices comply with Suruhanjaya Tenaga (ST) regulations and DOSH standards.- Project Oversight: Manage electrical upgrades, energy efficiency initiatives, and the installation of new machinery.
福利制度
- Annual Leave 12 days
- 13th months salary
- Accommodation provided
- Higher than industry average performance bonus
- Outpatient Medical (including spouse and dependent) and Dental benefit (Employee only)
- Group hospitalization (including spouse and dependent) and Group Personal Accident (Employee only)
- Public holiday falls on a Saturday, one day is credited to the leave creditsInstrumentation & UPS Engineer (Bentong)ID:59353
7,000 MYR ~ 10,000 MYRPahang工作内容
1. Instrumentation & Process Control- Maintain, calibrate, and troubleshoot process instrumentation, including: Temperature, pressure, flow, level, load cells, pH, conductivity, and speed sensors- Ensure accuracy and repeatability of instruments affecting: Extrusion, Coagulation, Curing, Cooling, Take-up and winding systems- Support PLC, HMI, and SCADA systems in coordination with automation teams- Diagnose signal issues and minimize false alarms- Participate in process optimization, stability improvement, and root cause analysis (RCA)2. UPS & Power Quality Systems- Commission, maintain, troubleshoot and monitor UPS systems supporting: Production lines, PLCs, SCADA servers, Control panels- Perform: Battery health checks, Load testing, Preventive maintenance, Failure simulations- Ensure seamless power transition during: Power dips, Blackouts, Generator changeovers- Coordinate UPS capacity planning for plant expansions and new lines3. Preventive & Corrective Maintenance- Develop and execute Preventive Maintenance (PM) schedules for: Instruments, UPS units, Sensors and transmitters- Respond to instrument and power-related breakdowns with minimum downtime- Maintain critical spares inventory and replacement strategy4. Compliance, Documentation & Standards- Ensure compliance with: Electrical safety standards, Calibration and QA requirements, ISO / customer audit expectations- Maintain: Calibration records, Loop diagrams, UPS single-line diagrams, Instrument data sheets- Support internal and external audits5. Project & Improvement Support- Support new equipment installation, commissioning, and FAT/SAT- Participate in: New production line setup, Control upgrades, Energy and reliability improvement projects- Liaise with vendors, contractors, and OEMs for troubleshooting and upgrades
福利制度
- Annual Leave 12 days
- 13th months salary
- Accommodation provided
- Higher than industry average performance bonus
- Outpatient Medical (including spouse and dependent) and Dental benefit (Employee only)
- Group hospitalization (including spouse and dependent) and Group Personal Accident (Employee only)
- Public holiday falls on a Saturday, one day is credited to the leave creditsOperation Service Engineer (RF) ID:59324
10,000 MYR ~ 12,000 MYRBayan Lepas工作内容
• On-Site Support & Maintenance:- Perform daily maintenance, troubleshooting, and rapid resolution of issues related to RF test systems to maximize production line availability.- Communicate closely with the factory’s production, test, and quality teams to address test-related issues in a timely manner.- Support product introduction by deploying, installing, integrating, and validating RF test systems (including test instruments, switching systems, and software) at the factory site.- Implement upgrades and modifications to existing test systems based on engineering change requests. • Test line Setup & Optimization:- Develop, debug, and maintain automation machine.- Continuously optimize test procedures and algorithms to improve test efficiency (UPH), reduce costs, and enhance test coverage and accuracy.- Collect and analyze production test data to identify trends and anomalies.- Prepare daily/weekly reports and provide data-driven insights for product and process improvement.- Assist the client in yield analysis and improvement by identifying root causes of test failures.- Train the operators and technicians on system operation and basic maintenance.- Create and update technical documentation, including system configuration manuals, maintenance guides, and troubleshooting procedures.
福利制度
Salary: RM10,000 - RM12,000
AL: Starting from 14 days
MC: 14 / 18 / 22 days
<Other benefits>
• Meal subsidy
• Fixed allowances: Phone, transport
• After confirmation: Medical insurance, health screening, dental/optical (They will share more during interview session)
