175个职位: Manufacturing(Electronics/Semiconductors)
Firmware EngineerID:59789
3,800 MYR ~ 6,800 MYRShah Alam工作内容
- Develop firmware programming for indoor and outdoor units of air-conditioner models using C Programming Language and Assembly Language. - Evaluate the developed firmware program through various stages of detailed testing, debugging, simulation and actual unit testing. - Build simple test circuits to evaluate the program through simulation. - Prepare documentation for the developed firmware programming. - Build Strong teamwork between inter-related R&D sections in developing air-conditioner models
福利制度
-Salary: RM3,800 - 6,800
- Annual Leave (15 days)
- Medical Leave (14 days)
- EPF & Sosco,
- Medical Insurance
- Group Term Life Insurance
- Free Parking
- Inhouse Cafeteria
- Inhouse Clinic
- Annual Increment
- Bonus (subject to company performance)Sales ExecutiveID:59775
4,000 MYR ~ 5,000 MYRNilai工作内容
- Managing a group of existing customers and at the same looking for opportunity todevelop new customer / market- Liaising with Japan HQ, Malaysia plant & other countries affiliates on sales/customerrelated matters- Sales & marketing activities for existing customers and developing newmarket/customers.- meeting with clients virtually or sales visits to customers.- demonstrating and presenting products for customer application.- Preparing bi-weekly sales forecast and annual sales budget.- attending trade exhibitions, conferences and meetings.- reviewing sales KPI performance.- negotiating contracts and packages
福利制度
- Bonus(1~1.5, depends on the performance)
- EPF, SOCSO, EIS provided
- AL：
14 days (Less than 2 years),
16 days (More than 2 years, less than 5 years)
20 days (More than 5 years)
- MC：
14 days (Less than 2 years)
18 days (More than 2 years but less than 5 years)
22 days (More than 5 years)
- Transportation Allowance(RM370~420Fixed)
- Internet Allowance (RM30 Fixed)
- For business trip car mileage claim is MYR 0.55/KM and highway toll claim as receiptSenior/Staff Digital Design EngineerID:59719
20,000 MYR ~ 25,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
This role will be responsible for architecting, designing, and verifying complex digital IPs and subsystems for SoCs or ASIC/FPGA-based products. As a senior role, it requires to work closely with system architects, verification, and physical design teams to deliver high-performance, power-efficient, and functionally correct RTL implementations. Overall, the responsibilities cover wider scope encompassing from IP to subsystem level and SOC level global issues.Key ResponsibilitiesArchitect with system engineers to perform:-• Define IP specifications, architecture & test concept.• Specify correct implementation of RTL design and verify digital circuits to deliver high performance, low power, and efficient implementation.• Conduct design reviews and support in documentation.• Support verification engineer to define verification test items.• Support in the roadmap formulation for the sensor IPs.• Support view generation engineers to verify the correctness of the Ips views.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment【Selangor】 Sales Engineer/Sales ExecutiveID:59720
3,000 MYR ~ 7,000 MYRShah Alam工作内容
• To explore and develop business opportunities with potential and existing customers;• Maintain good service level and rapport with existing and new customer;• Monitor Sales Performance, Competitors’ activities and AR collection• Self-driven to plan, strategize and execute all sales activities to achieve agreed sales target• Ability to acquire the products knowledge through products training and develop relevant knowledge techniques and skills to realise Sales• To follow up on all sales & marketing related matter in relation with both the company and customer.• To work in line and follow through with our company standard operating procedures• Other necessary duties / Special Events Duties.
福利制度
~RM3K - RM7K
- AL: 14, 17, 21 days
- ML: 14, 18, 22 days
- Insurance: Group PA insurance
- EPF/SOCSO
- Mileage, toll claim (subjective)Senior Staff Advanced Package & Board TeamID:59718
15,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
The Senior Staff Advanced Package & Board Team will lead the design, development, and implementation of advanced IC packaging and board-level solutions that enable high-performance, cost-effective, and reliable silicon products. This role requires strong technical leadership across multiple engineering domains — including substrate/interposer design, board design, SI/PI/thermal analysis, and manufacturing interface — while driving cross-functional collaboration with silicon design, system architecture, and OSAT/EMS partners.The successful candidate will define and execute the company’s packaging and board technology roadmap to support next-generation chiplet-based architectures, 2.5D/3D integration, and heterogeneous systems.Key Responsibilities1. Leadership & Strategy• Lead the Advanced Package & Board Design Team, including substrate, interposer, and PCB design engineers.• Define and execute packaging and board technology strategy aligned with company silicon product roadmap.• Establish design and verification methodologies for advanced packaging (e.g., 2.5D, fan-out, chiplet integration).• Drive innovation in thermal management, signal integrity, and power delivery optimization.2. Technical Execution• Oversee design and validation of interposers, substrates, and system boards from concept to production release.• Guide integration of chiplets, HBM, and passive components using state-of-the-art packaging technologies.• Ensure robust SI/PI, mechanical, and thermal analysis for design sign-off.• Collaborate with silicon design teams on bump assignment, die floorplanning, and package co-design.• Manage board-level design for system bring-up, test platforms, and reference designs.3. Supplier & Ecosystem Management• Engage and qualify OSATs, substrate vendors, and PCB manufacturers to ensure quality and yield.• Partner with EDA vendors to establish design automation flow and DRC verification.• Drive technology transfer and pilot runs with manufacturing partners.4. Project & People Management• Plan resources, schedules, and budgets to ensure timely delivery of packaging and board design projects.• Build and mentor a high-performing team with expertise across electrical, mechanical, and materials engineering.• Foster collaboration across silicon, test, reliability, and operations teams.
福利制度
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementLegal & Risk ManagerID:59706
12,000 MYR ~ 13,000 MYRKota Damansara/Petaling Jaya工作内容
■ JOB SUMMARYOverseeing the Legal and risk matters for the Group. You will be responsible for rendering support, expertise, and advice on various legal, regulatory, compliance, operational, contractual, and corporate legal matters to ensure the continued success of the company.The incumbent must be able to work independently, effectively, and in a fast-paced environment in line with the development in terms of business directions and objectives of the company.■ JOB RESPONSIBILITES1. Prepare, draft, and conduct a comprehensive review of contracts, agreements, letters, and legal documents arising from day-to-day business and operations, commercial and corporate matters, including corporate exercise, mergers and acquisitions, investments, commercial arrangements, collaborations and/or alliances, customer contracts, vendor/supplier contracts etc.2. Develop strategic approach and lead negotiations with counterparties to achieve the best possible options or positions in contract negotiations for the company.3. Analyze and address legal issues, and provide legal advice, and appropriate solutions.4. Safeguard the company against legal risks and violations.5. Participate and lead internal risk and assessment activities.6. Evaluate company procedures and reports to identify concealed or potential risks.7. Create, review, and enhance the company policies and procedures, ensuring implementation and compliance with the rules and regulations.8. Establish documentation system for the safe custody of legal documents and easy retrieval.9. To ensure effective communications with internal and external stakeholders of the Group of companies.10. To undertake any other tasks and assignments directed at the discretionary of the superior.
福利制度
・Basic Salary = RM 12,000 ~ RM 13,000
・AL = <5Y 14d, >5Y 18d
・MC = <2Y 14d, 2~5Y 18d, >5Y 22d
・Group PA, H&S, Term Life Insurance coverage
・Outpatient Medical – RM700/Year
・Car Park provided
・Bonus based on performance
・Group Annual Dinner (join Penang group)Customer Engineer (Melaka) - Grinder ID:59685
3,000 MYR ~ 4,500 MYRMalacca工作内容
- As first responder for all machine issues (machine installation, troubleshooting, maintenance)- Conduct machine training (operation, maintenance, basic application) to customer (engineer, technician and operator)- Provide guidance to engineer/operator/technician on how to fully utilize machine and its integrated function, to maximize machine performance capability- Plan, schedule and execute machine improvement activities (MTBA, OEE improvements, error reductions, conduct preventive maintenance)- Act as technical/engineering interface for Sales and Application members
福利制度
- Car allowance
- 13th month Bonus
- Mileage Claim (overseas/other state) : standardized payment
- Health Screening
- Dental
- company tripSales Executive ID:59660
3,000 MYR ~ 4,500 MYRGeorgetown工作内容
- Sales activity for Automotive/Electronic product customers.(Almost for existing customers)- Sales channel development with distributors- Yearly/Monthly Sales planning
福利制度
*Salary : RM3000-RM4500
*Incentive : Bonus (Increment)
*Allowance : Responsibility & Transport
(Car park fee will be provided, located near to office)
*EPF, Welfare are appliedSr Standard Cell Design EngineerID:59656
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Library Design Engineer to own the end-to-end development of a production-grade standard cell library on leading-edge process nodes. You will drive transistor-level design, multi-Vt cell topology, full characterization, and PPA validation delivering robust, sign-off-ready library views to downstream implementation flows. Seniority level to be determined by experience.Key Responsibilities• Design, simulate, and analyze standard cell circuits at transistor level, including combinational, sequential, clock, and physical utility cells across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths.• Perform layout process-node-shift; guide layout clean-up effort and review for DRC/LVS compliance, EM/IR rules, and parasitic awareness at the cell level.• Define & execute characterization flow to generate complete library views & models, covering timing (NLDM/CCS/ECSM), power (dynamic, leakage, internal), noise, and variation-aware models (LVF/SOCV/POCV); ensure Liberty, LEF, and GDS consistency.• Define & execute QA regression to check library quality; validate cell robustness including noise margin, drive strength, X-propagation, and scan/DFT cell correctness; drive STA correlation using PrimeTime or Tempus to confirm model accuracy in real PD flows.• Lead standard cell library IP integration into Testchip, including Testchip circuit and test plan development; support hardware bring-up and debug.• Perform pre/post-silicon correlation & model/design optimization; drive root-cause analysis for first-silicon issues and implement yield/robustness improvements.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Analog Circuit Design Engineer (Clocking)ID:59653
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/Puchong工作内容
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in Clocking as described below. Seniority level to be determined by experience.Key Responsibilities• Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted).• Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting.• Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques.• DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
福利制度
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
