Digital IC Design Verification Engineer ID:39687
|Salary||Monthly Salary 4,500MYR 〜 8,000MYR|
|Job Description||* Strong background in ASIC design flow (RTL to GDS)
* Strong coding skill in VERILOG/VHDL for synthesis able RTL and behavioral modeling, system verilog, Verilog - AMS is a plus.
* Working experience in FPGA design, debugging.
* Strong verification skills using SVA, UVM, OVM, DFT
* Scripting language experience a plus (perl, makefile,bash,tcl,...etc)
* Familiar with C coding, MATLAB is a plus
* Familiar with ECO Flow, FMEA is a plus
* Able to work independently and in team environment. Able to lead projects/team.
|Required Qualifications||Language : English
Education Background : Graduates from Electrical Engineering or Computer Science
Experience: Minimum 5 Years experience
- Strong background in ASIC design methodology and EDA tools for simulation and verification, synthesis, P&R, formal verification and static timing analysis.
- Strong coding skill in verilog/VHDL RTL and behavioral code, experience with system verilog will be plus.
- Experience with design trough complete from RTL and GDS flow and familiar with ECO flow.
- Familiar with Linux Environment (including shell scripting and linux gnu tools). Scripting language experience a plus ( perl, ruby, tcl, etc)
- Have successfully defined, developed and implemented digital logic. Familiarity with Cadence/ Mentor Graphics/ Synopsys environment is a plus. Working experience in FPGA design and development software.
- Highly self-motivated and excellent in problem solving and time management skills.
Age: 28 - 45
Gender : Open
Others :Ability to travel is a plus. Able to work independently and in team environment.
|Holidays||18 days AL
18 days Medical Leave
|Welfare||Accomodation allowance RM 800 (Foreginer only)
Transport allowance RM 200
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