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Digital IC Design Verification Engineer ID:39687

Salary Monthly Salary 4,500MYR 〜 8,000MYR
Location
Job Description * Strong background in ASIC design flow (RTL to GDS)
* Strong coding skill in VERILOG/VHDL for synthesis able RTL and behavioral modeling, system verilog, Verilog - AMS is a plus.
* Working experience in FPGA design, debugging.
* Strong verification skills using SVA, UVM, OVM, DFT
* Scripting language experience a plus (perl, makefile,bash,tcl,...etc)
* Familiar with C coding, MATLAB is a plus
* Familiar with ECO Flow, FMEA is a plus
* Able to work independently and in team environment. Able to lead projects/team.
Holidays 18 days AL
18 days Medical Leave
Welfare Accomodation allowance RM 800 (Foreginer only)
Transport allowance RM 200