概要

• 給与

  8,000 MYR ~ 35,000 MYR

• 業界

  Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

• 仕事内容

  Job Summary
  The Logic Design Engineer will be responsible for the architecture, design, implementation, and delivery of high-performance digital IPs and subsystems for ASIC/SoC products. The role involves microarchitecture definition, RTL development, functional validation support, timing convergence, and IP release activities while collaborating closely with architecture, verification, physical design, firmware, and system teams to achieve performance, power, area (PPA), and quality targets.
  
  The engineer will take ownership of IP or subsystem-level RTL implementation from specification through customer release and contribute to design quality through lint, CDC, formal verification, timing closure, and design reviews.
  
  Key Responsibilities
  1. RTL Design & Microarchitecture
  • Define and implement block-level or subsystem-level RTL architecture based on product specifications.
  • Develop high-quality RTL using Verilog/SystemVerilog for ASIC/SoC products.
  • Participate in microarchitecture definition and document design decisions.
  • Ensure RTL complies with coding standards, synthesis guidelines, and design methodologies.
  • Review RTL implementation and participate in peer design reviews.
  
  2. Digital IP Development
  • Own assigned digital IPs or logic blocks from specification through implementation and release.
  • Design high-speed digital logic capable of achieving timing closure on advanced process nodes.
  • Collaborate with architects, firmware, and system engineers to ensure correct feature implementation.
  • Support IP integration into subsystem or SoC environments.
  
  3. Design Quality & Verification Support
  • Produce functional test plans covering design requirements.
  • Support Design Verification teams in debugging simulation failures and functional issues.
  • Perform and resolve: Lint, CDC/RDC, Formal Equivalence Verification (FEV), Low Power (UPF/CPF)
  • Participate in coverage closure and verification reviews.
  
  4. Timing & Design Closure
  • Work closely with Physical Design and STA teams to achieve timing closure.
  • Support synthesis, timing optimization, clock-domain crossing, and low-power implementation.
  • Develop and validate timing constraints (SDC) and power intent where applicable.
  • Resolve setup/hold timing issues and support floorplan optimization.
  
  5. IP Release & Documentation
  • Own IP release deliverables including RTL packages, documentation, and quality sign-off.
  • Prepare design documentation, architecture specifications, and implementation reports.
  • Ensure all deliverables meet internal quality standards and customer requirements.
  
  6. Cross-functional Collaboration
  • Work closely with Architecture, DV, Physical Design, Firmware, Validation, and System Engineering teams.
  • Participate in design reviews, technical discussions, and project planning.
  • Contribute to continuous improvement of RTL design methodology and automation flows.