Design Automation Engineer (Analog/Mixed-Signal IP)ID:60081

8,000 MYR ~ 16,000 MYRバヤン・レパス Bayan Lepas約10時間 前

概要

  • 給与

    8,000 MYR ~ 16,000 MYR

  • 業界

    Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

  • 仕事内容

    We are seeking a Design Automation (DA) Engineer to develop, deploy, and maintain EDA flows, scripting infrastructure, and methodology tooling that accelerate the full lifecycle of analog/mixed-signal IP — from schematic capture and simulation through physical verification, characterization, and customer delivery. The DA Engineer works as an embedded enablement partner to circuit and layout designers, translating manual, repetitive, and error-prone tasks into robust, scalable automation. Seniority level to be determined by experience.

    Key Responsibilities
    • Develop and maintain simulation automation and regression flows using ADE-XL/Assembler, Spectre, and/or HSPICE; implement corner, Monte Carlo, and mismatch batch runs, compare results against specification limits, and report pass/fail status to designers.
    • Develop SKILL/SKILL++ and Python scripts to automate repetitive layout operations: parameterized cell (PCell) authoring, constraint-driven routing, DRC-clean template generation, and pre-tapeout LVS/DRC batch checking.
    • Own and maintain the physical verification flow: Calibre DRC/LVS/xRC, Pegasus/PVS, and/or Quantus QRC extraction; automate rule deck updates following foundry process revisions, and maintain a documented automated waiver management system.
    • Develop and maintain IP characterization flows; automate Liberty (.lib) timing/power view generation, IBIS model extraction, and datasheet/specification reporting pipelines for customer delivery.
    • Support PDK qualification and updates: validate simulation model files, verify PCell correctness after foundry PDK revisions, and communicate technology node constraints (layout-dependent effects, advanced-node DRC restrictions) to circuit and layout designers.
    • Serve as the primary DA support contact for circuit and layout designers: diagnose tool issues, resolve flow bottlenecks, provide training on automation scripts and new methodologies, and continuously improve designer experience based on feedback.
    • Manage EDA tool installation, licensing, compute cluster job submission, and tool vendor engagement for issue escalation, new tool evaluation, and methodology co-development.

求めている人材

  • 応募条件

    • BS/MS in Electrical/Electronics Engineering, Computer Engineering, or related field.
    • Typically 3–5+ years of hands-on EDA/CAD engineering or design automation experience in an analog, mixed-signal, or custom IC design environment.
    • Proficiency in scripting and programming for EDA automation: SKILL/SKILL++, Python (NumPy/SciPy/Pandas/Matplotlib), Tcl, and bash/csh shell scripting; ability to write maintainable, well-documented tools that other engineers can adopt and extend independently.
    • Working knowledge of industry-standard AMS EDA tools (Cadence Virtuoso, Spectre/ADE-XL or HSPICE, Calibre DRC/LVS/xRC, Quantus QRC or StarRC) combined with sufficient analog circuit understanding to read schematics, interpret simulation results, and distinguish tool failures from design issues.
    • Experience with design data management: OA library structures, version control, and IP release packaging conventions (GDS, LEF, CDL, Liberty, IBIS).
    • Strong problem-solving skills and attention to detail; ability to manage multiple concurrent tasks, communicate proactively to design leads, and document automation flows clearly for team adoption.

    Preferred / Nice-to-Have Experience
    • Experience with IP characterization and library view generation: Liberty (.lib) syntax, IBIS/IBIS-AMI modeling, and automated datasheet generation pipelines targeting customer delivery packages.
    • Familiarity with Python-based layout automation frameworks: BAG (Berkeley Analog Generator), gdstk/gdspy, or equivalent approaches for parametric analog cell generation that is portable across technology nodes.
    • Exposure to FinFET (7/5/3 nm) or advanced-node process constraints as they affect automation: fin quantization, gate-cut rules, single-diffusion break (SDB/DDB), and advanced metal routing restrictions relevant to PCell and template design.
    • Prior analog/mixed-signal domain exposure (e.g., clocking, I/O, or power management circuits) sufficient to understand the simulation corner sets, analysis flows, and sign-off criteria relevant to the IP blocks being automated.
    • Familiarity with compute infrastructure for EDA job scheduling, HPC cluster administration, EDA license server management.

  • 英語

    -

  • その他言語

    English

その他