RTL Design EngineerID:53631

6,000 MYR ~ 12,000 MYRBayan Lepas7日 ago

概述

  • 薪资

    6,000 MYR ~ 12,000 MYR

  • 产业类别

    Software/Information Processing, IT/Telecommunications, Consulting

  • 工作内容

    • Performing concept studies and provide direction in terms of performance, gate count and power for various digital designs.
    • Writing detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers.
    • Providing high-quality RTL description, including assertions, for the design.
    • Formal tools and static checkers will be used to guarantee RTL quality.
    • Supporting design verification to insure bug-free first silicon.
    • Driving functional and code coverage as well as timing closure for your designs.
    • Supporting silicon bring-up, performance and power characterization

资格

  • 应征条件

    - Education Background : Diploma/ Bachelor Degree in Computer Science, Internet Technology, Hardware Engineering and other equivalent studies.
    - Experience : Minimum have 4 year working experience in RTL
    - Require Skill : RTL design using Verilog or System Verilog, assertion writing is Mandatory
    - Design of state machines, data paths, arbitration and clock domain crossing logic
    - Logic synthesis, timing constraints
    - Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL
    - Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking
    - Prior experience in DDR PHY design and mixed-signal environment is a plus

    Contact us:
    1. Send in your latest resume to info-my@reeracoen.asia

  • 英文

    -

  • 其他语言

    Mandarin, English

附加信息

相关职缺