Memory IP Architect / SoC uArchitectID:61253

8,000 MYR ~ 35,000 MYRバヤン・レパス Bayan Lepas約14時間 前

概要

  • 給与

    8,000 MYR ~ 35,000 MYR

  • 業界

    Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

  • 仕事内容

    Role Overview
    We are seeking a Senior Design Engineer specializing in Network-on-Chip (NoC) to join our cutting-edge semiconductor team. This role involved architecting, designing, and optimizing NoC interconnect solutions for high-performance chips. You will work closely with architects, verification engineers, and software teams to deliver scalable, efficient, and low-latency interconnect designs.

    Key Responsibilities
    • NoC Architecture & Design: Develop and optimize high-performance, scalable, and low-latency NoC solutions for SoCs and multi-core processors, components, ensuring performance, area, and power efficiency.
    • Performance Analysis: Conduct traffic modeling, simulation, and bottleneck analysis to optimize NoC throughput and latency.
    • Verification & Validation: Collaborate with verification teams to develop testbenches, ensure functional correctness, and debug issues.
    • Power & Area Optimization: Optimize NoC designs for low-power and area-efficient implementations, working closely with physical design teams.
    • Integration & Customization: Work on custom NoC configurations, integrating third- party IPs, and tailoring interconnect solutions for specific applications.
    • Tool & Flow Development: Enhance NoC design methodologies by developing scripts, automation flows, and performance monitoring tools.
    • Cross-functional Collaboration: Work with chip architects, backend engineers, and software teams to define NoC requirements and optimize for real-world workloads.

求めている人材

  • 応募条件

    • Bachelor’s/Master’s/PhD in Electrical Engineering, Computer Engineering, or related field.
    • At least 3 years experience in NOC RTL Design or experience in RTL Design, bonus if has interconnect architectures
    • Strong expertise in Verilog/SystemVerilog RTL design and synthesis-friendly coding.
    • Hands-on experience with NoC topologies (mesh, ring, torus, crossbar, etc.) and flow control techniques.
    • Proficiency in performance modeling, simulation, and debugging.
    • Experience with industry-standard EDA tools for synthesis, static timing analysis (STA), and power analysis.
    • Strong understanding of on-chip communication protocols (AXI, CHI, PCIe, CXL, etc.).
    • Excellent problem-solving skills and ability to work in a fast-paced, collaborative environment.

    Preferred:
    • Experience with NoC-specific tools (Arteris, NetSpeed, OpenSoC, etc.).
    • Familiarity with cache coherence protocols (MESI/MOESI, CCIX, etc.).
    • Knowledge of hardware security, fault tolerance, and reliability in NoC design.
    • Scripting skills (Python, Perl, Tcl) for automation and debugging.
    • Experience with chiplet interconnects and heterogeneous computing architectures.

  • 英語

    -

  • その他言語

    English

その他