Memory IP Architect / SoC uArchitectID:61252

8,000 MYR ~ 35,000 MYRバヤン・レパス Bayan Lepas約14時間 前

概要

  • 給与

    8,000 MYR ~ 35,000 MYR

  • 業界

    Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

  • 仕事内容

    We are looking for an experienced Memory IP Architect / uArchitect to lead the architecture and development of next-generation memory solutions for AI, HPC, networking, and custom ASIC applications.

    This role will drive the definition of memory subsystems, memory controllers, and high-performance SoC memory solutions from concept through silicon.

    Responsibilities
    • Define architecture and specifications for Memory IP and SoC subsystems.
    • Lead memory architecture for DDR5, LPDDR5X/LPDDR6, HBM3E/HBM4, and cache subsystems.
    • Drive architecture trade-offs across performance, power, area, and cost.
    • Develop performance models and conduct architecture exploration.
    • Define memory hierarchy, and system-level optimization strategies.
    • Collaborate with RTL, DV, DFT, PD, Packaging, Firmware, and Software teams.
    • Support customer engagements, technical reviews, and roadmap planning.
    • Guide implementation through silicon bring-up and performance tuning.

求めている人材

  • 応募条件

    • BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
    • At least 10 years of semiconductor industry experience.
    • Proven track record delivering complex SoCs or Memory IP from architecture definition to silicon.
    • Strong expertise in several of the following:
    o DDR5 / LPDDR5X / LPDDR6
    o HBM3E / HBM4
    o SRAM and Cache Architecture
    o Memory Controllers and PHY
    o Memory Coherency
    o AI Accelerator or HPC Architecture
    • Experience with architectural modeling using C/C++, SystemC, or Python.

  • 英語

    -

  • その他言語

    English

その他