Logic Design EngineerID:60086

10,000 MYR ~ 22,000 MYRバヤン・レパス Bayan Lepas1日 前

概要

  • 給与

    10,000 MYR ~ 22,000 MYR

  • 業界

    Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

  • 仕事内容

    We are seeking a Logic Design Engineer to implement RTL design. Familiarity with LPDDR and HBM memory interface IP will be a plus. The engineer will own block-level microarchitecture, RTL coding, and design sign-off from specification through customer delivery. Seniority level to be determined by experience.

    Key Responsibilities
    • Define and implement block-level and layer-level RTL for various IPs, meeting high-frequency timing requirements at advanced process nodes.
    • Drive microarchitecture definition for assigned blocks in collaboration with senior architects; document design decisions and trade-offs clearly for cross-functional review.
    • Achieve timing closure at high frequencies; work with physical design and STA teams to resolve setup/hold violations, manage clock domain crossings (CDC), and support floorplan iterations.
    • Execute design quality checks: CDC analysis, lint (Lintra), formal equivalence verification (FEV), and low-power (UPF) flows; resolve violations to achieve clean convergence.
    • Produce and review test plans for block-level functional verification, including black-box and white-box simulation, FPV, and emulation; collaborate with DV engineers to resolve design bugs.
    • Own IP release deliverables for customer handoff: RTL packages, netlists, and accompanying documentation; ensure release quality and compliance with customer specification.

求めている人材

  • 応募条件

    • BS/MS in Electrical/Electronics Engineering, Computer Engineering, or related field.
    • 4~5+ years of hands-on experience in digital logic design and RTL coding; experience in memory interface IP (DDR, LPDDR, or HBM) is strongly preferred.
    • Strong proficiency in SystemVerilog/Verilog RTL; ability to write synthesis-clean, lint-clean, and CDC-clean code at high clock frequencies on FinFET process nodes.
    • Experience with design quality flows: CDC (Questa CDC, SpyGlass), lint (Lintra/SpyGlass), formal verification (JasperGold/VC Formal), and low-power (UPF/CPF).
    • Scripting ability in Python, Tcl, or Perl for design flow automation; familiarity with synthesis (DC/Genus) and STA (PrimeTime/Tempus) toolchains.
    • Strong problem-solving skills; ability to collaborate effectively with architecture, DV, PD, and customer teams across project milestones.

    Preferred / Nice-to-Have
    • Understanding of JEDEC memory protocols (LPDDR or HBM); familiarity with DFI interface, PHY-controller partitioning, and memory subsystem architecture.
    • Direct experience with LPDDR/HBM controller or PHY digital logic design, including channel retry, ECC, and power management features.
    • Exposure to FPGA prototyping or pre-silicon emulation platforms (Palladium, Zebu) for memory controller bring-up and validation.
    • Background in low-power design techniques (clock gating, power gating, DVFS) applicable to mobile-class LPDDR subsystems.

  • 英語

    -

  • その他言語

    English

その他