Principle Digital Design EngineerID:59118

20,000 MYR ~ 25,000 MYRバヤン・レパス Bayan Lepas6日 前

概要

  • 給与

    20,000 MYR ~ 25,000 MYR

  • 業界

    Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

  • 仕事内容

    This role will be responsible for architecting, designing, and verifying complex digital IPs and subsystems for SoCs or ASIC/FPGA-based products. As a senior role, it requires to work closely with system architects, verification, and physical design teams to deliver high-performance, power-efficient, and functionally correct RTL implementations. Overall, the responsibilities cover wider scope encompassing from IP to subsystem level and SOC level global issues.

    Key Responsibilities
    Architect with system engineers to perform:-
    • Define IP specifications, architecture & test concept.
    • Specify correct implementation of RTL design and verify digital circuits to deliver high performance, low power, and efficient implementation.
    • Conduct design reviews and support in documentation.
    • Support verification engineer to define verification test items.
    • Support in the roadmap formulation for the sensor IPs.
    • Support view generation engineers to verify the correctness of the Ips views.

求めている人材

  • 応募条件

    • Bachelor’s or Master’s degree in Electronic Engineering.
    • At least 10 years of experience in ASIC/FPGA digital design.
    • Strong knowledge of RTL design using SystemVerilog/Verilog.
    • Deep understanding of SoC design flow, including synthesis, timing, power, and verification.
    • Familiar with AMBA bus protocols (AXI/AHB/APB).
    • Experience with EDA tools (Synopsys, Cadence, Mentor).
    • Excellent debugging and problem-solving skills.
    • Strong communication and documentation abilities.

  • 英語

    -

  • その他言語

    English

その他