Sr Analog Circuit Design Engineer (General Purpose I/O) (GPIO)ID:59654

8,000 MYR ~ 16,000 MYRバヤン・レパス Bayan Lepas約11時間 前

概要

  • 給与

    8,000 MYR ~ 16,000 MYR

  • 業界

    Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

  • 仕事内容

    We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in GPIO (General Purpose I/O) design as described below. Seniority level to be determined by experience.

    Key Responsibilities
    • Own GPIO IP architecture/specs: bidirectional I/O, mixed-voltage/failsafe tolerance, programmable drive strength & slew-rate control, Schmitt-trigger inputs, pull-up/pull-down, bus-keeper/retention, and pad-ring support cells (supply, corner, filler, terminator/diode-breaker, cut cells).
    • Design and implement transistor-level GPIO circuits: input receiver, output driver, level shifters, predrivers, reference/compensation sub-blocks, analog test hooks.
    • Ensure robust reliability and quality signoff for I/O cells and rings (ESD, latch-up, EM/IR, aging, overstress, noise immunity and ground-bounce/SSN considerations).
    • Run comprehensive simulations and verification (PVT corners/Monte Carlo, pre- and post-layout, worst-case timing and functional modes) and drive design reviews with clear documentation.
    • Develop and release collateral for IP enablement: datasheets, integration guidelines, characterization reports, and models (SPICE/Verilog-A, and IBIS where applicable).
    • Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
    • Perform SI/PI and I/O behavior checks at the package/board interface level; support IBIS-based signoff and customer debug as needed.

求めている人材

  • 応募条件

    • BS/MS in Electrical/Electronics Engineering (or related).
    • Typically 3-6+ years of relevant experience in analog/mixed-signal IC design.
    • Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects.
    • Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain.
    • Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment.

    Preferred / Nice-to-Have Experience
    • Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).
    • Experience creating SI collateral (e.g., IBIS/IBIS-AMI) and/or contributing to timing closure flows (e.g., PrimeTime or equivalent) is a plus.

  • 英語

    -

  • その他言語

    English

その他