概要

• 給与

  10,000 MYR ~ 22,000 MYR

• 業界

  Software/Information Processing, IT/Telecommunications, Manufacturing(Computer/Telecommunication), Manufacturing(Electronics/Semiconductors)

• 仕事内容

  We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in Clocking as described below. Seniority level to be determined by experience.
  
  Key Responsibilities
  • Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted).
  • Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting.
  • Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques.
  • DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks.
  • Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.
  • Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions.
  • Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.
  • Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.
  • Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.
  • Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.