Place and Route EngineerID:39686

4,500 MYR ~ 8,000 MYRKulim3ヶ月以上前

概要

  • 給与

    4,500 MYR ~ 8,000 MYR

  • 業界

    Manufacturing(Electronics/Semiconductors)

  • 仕事内容

    * Through understanding of detailed analog circuit design and the ability to design independently various functional blocks.
    * Detailed knowledge in the design and operation of the following analog blocks
    * Basic Analog building blocks (op amps, comparators, current sources, current mirrors, voltage references)
    * Power Management blocks ( band gap references, linear regulators, DC-DC converter of various topologies, LDOs)
    * System level protection blocks (UVLO, POR, OTP, short circuit protection etc)
    * PLL and transceiver blocks (output drivers, multiplexer and de-multiplexer, clock generator, equalizers, clock and data recovery, frequency
    detectors, oscillators, filters)
    * ADCs and DACs
    * In-depth understanding of leading process technologies such as sub-micron CMOS, BiCMOS/DMOS, BCD, HV
    * Experience with design practices such as minimizing device mismatch, noise, signal coupling, ESD, latchup and device SOA is a must.
    * Experience with simulation tools required to efficiently simulate analog/mixed signal circuits e.g spectre, ultrasim, hspice, etc
    * Understanding of simulations models, design rules and verification procedures (DRC/ LVS/ERC is essential.
    * Modeling and design skills in Verilog- A/ Verilog -AMS and system modeling with Mathlab are an added advantage.
    * Experience in IO Interface circuit design and analysis
    * Exposed to high speed IOs e.g. USB2, LVDS, PCIE , Serdes, MIPI

求めている人材

  • 応募条件

    Language: English
    Education:Degree in Electrical Engineering
    Experience:
    - 3-5 Years professional experience in microelectronics physical implementation.
    - Experience in low-power design techniques
    - Good understanding of ERC, EMI Rules and impact on final chip verification and cycle time reduction.
    - Ability to work in a team environment and participate in cross- functional activities.
    Required skills:
    - Good Verbal and writing communication skills. Fabrication process variation impacts and performance.
    - Cadence RTL compiler, SOC- Encounter/ EDIS, ETS, EPS. (Mandatory)
    - Mentor Calibre / Assura (Desirable)
    Certificate: N/A
    Age: 28 - 45
    Gender: Open
    Other: N/A

  • 英語

    -

  • その他言語

    Malay, Hindi, Mandarin

その他